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sys/arm64/qoriq/clk/qoriq_clkgen.c

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/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2020 Alstom Group.
* Copyright (c) 2020 Semihalf.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/endian.h>
#include <sys/rman.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/module.h>
#include <sys/mutex.h>
#include <machine/bus.h>
#include <dev/fdt/simplebus.h>
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#include <dev/extres/clk/clk_fixed.h>
#include <arm64/qoriq/clk/qoriq_clkgen.h>
#include "clkdev_if.h"
MALLOC_DEFINE(M_QORIQ_CLKGEN, "qoriq_clkgen", "qoriq_clkgen");
static struct resource_spec qoriq_clkgen_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ -1, 0 }
};
static const char *clk_names[] = {
"sysclk",
"cmux",
"hwaccel",
"fman",
"pltfrm"
};
static int
qoriq_clkgen_ofw_mapper(struct clkdom *clkdom, uint32_t ncells,
phandle_t *cells, struct clknode **clk)
{
char namebuf[QORIQ_CLK_NAME_MAX_LEN];
if (ncells != 2)
return (EINVAL);
if (cells[0] > 4)
return (EINVAL);
/* Use clock node names for lookup. */
mmelUnsubmitted
Not Done
Inline Actions

[1]
Should be in qoriq_clkgen.h:

#define	QORIQ_CLK_ID(_type, _index) (((_type) << 8) +(_index))

and here :

/* Use clock node id for lookup. */
*clk = clknode_find_by_id(QORIQ_CLK_ID(cells[0], cells[1]));
mmel: [1] Should be in qoriq_clkgen.h: ``` #define QORIQ_CLK_ID(_type, _index) (((_type) << 8) +…
snprintf(namebuf, QORIQ_CLK_NAME_MAX_LEN, "cg-%s-%d",
clk_names[cells[0]], cells[1]);
*clk = clknode_find_by_name(namebuf);
if (clk == NULL)
return (EINVAL);
return (0);
}
static int
qoriq_clkgen_write_4(device_t dev, bus_addr_t addr, uint32_t val)
{
struct qoriq_clkgen_softc *sc;
sc = device_get_softc(dev);
if (sc->flags & QORIQ_LITTLE_ENDIAN)
bus_write_4(sc->res, addr, htole32(val));
else
bus_write_4(sc->res, addr, htobe32(val));
return (0);
}
static int
qoriq_clkgen_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
{
struct qoriq_clkgen_softc *sc;
sc = device_get_softc(dev);
if (sc->flags & QORIQ_LITTLE_ENDIAN)
*val = le32toh(bus_read_4(sc->res, addr));
else
*val = be32toh(bus_read_4(sc->res, addr));
return (0);
}
static int
qoriq_clkgen_modify_4(device_t dev, bus_addr_t addr, uint32_t clr,
uint32_t set)
{
uint32_t reg;
qoriq_clkgen_read_4(dev, addr, &reg);
mmelUnsubmitted
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Modify operation should follow QORIQ_LITTLE_ENDIAN flag.

mmel: Modify operation should follow QORIQ_LITTLE_ENDIAN flag.
reg &= ~clr;
reg |= set;
qoriq_clkgen_write_4(dev, addr, reg);
return (0);
}
static void
qoriq_clkgen_device_lock(device_t dev)
{
struct qoriq_clkgen_softc *sc;
sc = device_get_softc(dev);
mtx_lock(&sc->mtx);
}
static void
qoriq_clkgen_device_unlock(device_t dev)
{
struct qoriq_clkgen_softc *sc;
sc = device_get_softc(dev);
mtx_unlock(&sc->mtx);
}
static device_method_t qoriq_clkgen_methods[] = {
DEVMETHOD(clkdev_write_4, qoriq_clkgen_write_4),
DEVMETHOD(clkdev_read_4, qoriq_clkgen_read_4),
DEVMETHOD(clkdev_modify_4, qoriq_clkgen_modify_4),
DEVMETHOD(clkdev_device_lock, qoriq_clkgen_device_lock),
DEVMETHOD(clkdev_device_unlock, qoriq_clkgen_device_unlock),
DEVMETHOD_END
};
DEFINE_CLASS_0(qoriq_clkgen, qoriq_clkgen_driver, qoriq_clkgen_methods,
sizeof(struct qoriq_clkgen_softc));
static int
qoriq_clkgen_create_sysclk(device_t dev)
{
struct qoriq_clkgen_softc *sc;
mmelUnsubmitted
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Modify operation should follow QORIQ_LITTLE_ENDIAN modifier.

mmel: Modify operation should follow QORIQ_LITTLE_ENDIAN modifier.
struct clk_fixed_def def;
const char *clkname;
phandle_t node;
clk_t sysclk;
int error;
sc = device_get_softc(dev);
node = ofw_bus_get_node(dev);
/* Create node referring to sysclk oscillator in current domain. */
mmelUnsubmitted
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this doesn't follow bindings (see /Documentation/devicetree/bindings/clock/qoriq-clock.txt
If "clock-frequency" is declared, you should create sysclk node itself as fixed clock with
given frequency. Otherwise , you should use 'sysclk' and (optionally) 'coreclk' as external as is defined in binding documentation.

mmel: this doesn't follow bindings (see /Documentation/devicetree/bindings/clock/qoriq-clock.txt If…
memset(&def, 0, sizeof(def));
def.clkdef.name = "cg-sysclk-0";
def.clkdef.id = 0;
def.clkdef.parent_cnt = 1;
def.mult = 1;
def.div = 1;
error = clk_get_by_ofw_name(dev, node, "sysclk", &sysclk);
if (error != 0) {
error = clk_get_by_ofw_index(dev, node, 0, &sysclk);
if (error != 0)
return (error);
}
clkname = clk_get_name(sysclk);
def.clkdef.parent_names = &clkname;
error = clknode_fixed_register(sc->clkdom, &def);
mmelUnsubmitted
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All this is unnecessary. You should use resoved name of 'sysclk' as parent name for platform pll and resolved name of 'coreclk' for core plls.

mmel: All this is unnecessary. You should use resoved name of 'sysclk' as parent name for platform…
return (error);
}
int
qoriq_clkgen_attach(device_t dev)
{
dgr_semihalf.comAuthorUnsubmitted
Done
Inline Actions

Here I left the code creating nodes in current clock domain. I think
that a better approach would be to save clock names in softc, but
this would require modifying clock interface as from what I've noticed
there is no way of accessing softc from ofw_mapper function. This would
only require adding device_t getter function for clkdom, however
I don't want to modify existing interfaces without someone more
experienced sharing their opinion.

dgr_semihalf.com: Here I left the code creating nodes in current clock domain. I think that a better approach…
mmelUnsubmitted
Not Done
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I don’t want to block you, so please take all bellow as discussion on implementation detail.
Please don’t map 2 different DT identifiers to one clock node, I think that this can create unexpected side effects on consumer side.
But, yeah, it seems that sysclk and/or coreclk can be referenced from other DT nodes when these are external, driven by other clock from other clock domain (see fsl-ls1043a.dtsi and clock definition for lpuart0 node). Then yes, these “phantom” 1:1 dividers are probably best solution. I did not noticed this previously, so sorry for noise. Only please, put this to short comment

mmel: I don’t want to block you, so please take all bellow as discussion on implementation detail.
struct qoriq_clkgen_softc *sc;
int i, error;
sc = device_get_softc(dev);
sc->dev = dev;
if (bus_alloc_resources(dev, qoriq_clkgen_spec, &sc->res) != 0) {
device_printf(dev, "Cannot allocate resources.\n");
return (ENXIO);
}
mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
sc->clkdom = clkdom_create(dev);
if (sc->clkdom == NULL)
panic("Cannot create clock domain.\n");
error = qoriq_clkgen_create_sysclk(dev);
if (error != 0) {
device_printf(dev, "Cannot create sysclk.\n");
return (error);
}
error = qoriq_clk_pll_register(sc->clkdom, sc->pltfrm_pll_def);
if (error != 0) {
device_printf(dev, "Cannot create platform PLL.\n");
return (error);
}
for (i = 0; i < sc->cga_pll_num; i++) {
error = qoriq_clk_pll_register(sc->clkdom, sc->cga_pll[i]);
if (error != 0) {
device_printf(dev, "Cannot create CGA PLLs\n.");
return (error);
}
}
/*
* Both CMUX and HWACCEL multiplexer nodes can be represented
* by using built in clk_mux nodes.
*/
for (i = 0; i < sc->mux_num; i++) {
error = clknode_mux_register(sc->clkdom, sc->mux[i]);
if (error != 0) {
device_printf(dev, "Cannot create MUX nodes.\n");
return (error);
}
}
if (sc->init_func != NULL) {
error = sc->init_func(dev);
if (error) {
device_printf(dev, "Clock init function failed.\n");
return (error);
}
}
clkdom_set_ofw_mapper(sc->clkdom, qoriq_clkgen_ofw_mapper);
if (clkdom_finit(sc->clkdom) != 0)
panic("Cannot finalize clock domain initialization.\n");
if (bootverbose)
clkdom_dump(sc->clkdom);
return (0);
}