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sys/dev/cadence/if_cgem_hw.h

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/* /*
* Hardware and register defines for Cadence GEM Gigabit Ethernet * Hardware and register defines for Cadence GEM Gigabit Ethernet
* controller such as the one used in Zynq-7000 SoC. * controller such as the one used in Zynq-7000 SoC.
* *
* Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
* (v1.4) November 16, 2012. Xilinx doc UG585. GEM is covered in Ch. 16 * (v1.4) November 16, 2012. Xilinx doc UG585. GEM is covered in Ch. 16
* and register definitions are in appendix B.18. * and register definitions are in appendix B.18.
*
* Additional Reference: Zynq UltraScale+ Device Register Reference
* (UG1087 v1.7 Feb 8,2019):
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* https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html
*/ */
#ifndef _IF_CGEM_HW_H_ #ifndef _IF_CGEM_HW_H_
#define _IF_CGEM_HW_H_ #define _IF_CGEM_HW_H_
/* Cadence GEM hardware register definitions. */ /* Cadence GEM hardware register definitions. */
#define CGEM_NET_CTRL 0x000 /* Network Control */ #define CGEM_NET_CTRL 0x000 /* Network Control */
#define CGEM_NET_CTRL_FLUSH_DPRAM_PKT (1 << 18) #define CGEM_NET_CTRL_FLUSH_DPRAM_PKT (1 << 18)
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#define CGEM_NET_STAT_PCS_AUTONEG_DUP_RES (1 << 3) #define CGEM_NET_STAT_PCS_AUTONEG_DUP_RES (1 << 3)
#define CGEM_NET_STAT_PHY_MGMT_IDLE (1 << 2) #define CGEM_NET_STAT_PHY_MGMT_IDLE (1 << 2)
#define CGEM_NET_STAT_MDIO_IN_PIN_STATUS (1 << 1) #define CGEM_NET_STAT_MDIO_IN_PIN_STATUS (1 << 1)
#define CGEM_NET_STAT_PCS_LINK_STATE (1 << 0) #define CGEM_NET_STAT_PCS_LINK_STATE (1 << 0)
#define CGEM_USER_IO 0x00C /* User I/O */ #define CGEM_USER_IO 0x00C /* User I/O */
#define CGEM_DMA_CFG 0x010 /* DMA Config */ #define CGEM_DMA_CFG 0x010 /* DMA Config */
#define CGEM_DMA_CFG_ADDR_BUS_64 (1 << 30)
#define CGEM_DMA_CFG_DISC_WHEN_NO_AHB (1 << 24) #define CGEM_DMA_CFG_DISC_WHEN_NO_AHB (1 << 24)
#define CGEM_DMA_CFG_RX_BUF_SIZE_SHIFT 16 #define CGEM_DMA_CFG_RX_BUF_SIZE_SHIFT 16
#define CGEM_DMA_CFG_RX_BUF_SIZE_MASK (0xff << 16) #define CGEM_DMA_CFG_RX_BUF_SIZE_MASK (0xff << 16)
#define CGEM_DMA_CFG_RX_BUF_SIZE(sz) ((((sz) + 63) / 64) << 16) #define CGEM_DMA_CFG_RX_BUF_SIZE(sz) ((((sz) + 63) / 64) << 16)
#define CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN (1 << 11) #define CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN (1 << 11)
#define CGEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL (1 << 10) #define CGEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL (1 << 10)
#define CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_1K (0 << 8) #define CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_1K (0 << 8)
#define CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_2K (1 << 8) #define CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_2K (1 << 8)
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#define CGEM_PTP_TX_NS 0x1E4 /* PTP Event Frame xmit ns */ #define CGEM_PTP_TX_NS 0x1E4 /* PTP Event Frame xmit ns */
#define CGEM_PTP_RX_S 0x1E8 /* PTP Event Frame rcv'd s */ #define CGEM_PTP_RX_S 0x1E8 /* PTP Event Frame rcv'd s */
#define CGEM_PTP_RX_NS 0x1EC /* PTP Event Frame rcv'd ns */ #define CGEM_PTP_RX_NS 0x1EC /* PTP Event Frame rcv'd ns */
#define CGEM_PTP_PEER_TX_S 0x1F0 /* PTP Peer Event xmit s */ #define CGEM_PTP_PEER_TX_S 0x1F0 /* PTP Peer Event xmit s */
#define CGEM_PTP_PEER_TX_NS 0x1F4 /* PTP Peer Event xmit ns */ #define CGEM_PTP_PEER_TX_NS 0x1F4 /* PTP Peer Event xmit ns */
#define CGEM_PTP_PEER_RX_S 0x1F8 /* PTP Peer Event rcv'd s */ #define CGEM_PTP_PEER_RX_S 0x1F8 /* PTP Peer Event rcv'd s */
#define CGEM_PTP_PEER_RX_NS 0x1FC /* PTP Peer Event rcv'd ns */ #define CGEM_PTP_PEER_RX_NS 0x1FC /* PTP Peer Event rcv'd ns */
#define CGEM_DESIGN_CFG1 0x280 /* Design Configuration 1 */
#define CGEM_DESIGN_CFG1_AXI_CACHE_WIDTH_MASK (0xfU << 28)
#define CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_MASK (7 << 25)
#define CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_32 (1 << 25)
#define CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_64 (2 << 25)
#define CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_128 (4 << 25)
#define CGEM_DESIGN_CFG1_IRQ_READ_CLR (1 << 23)
#define CGEM_DESIGN_CFG1_NO_SNAPSHOT (1 << 22)
#define CGEM_DESIGN_CFG1_NO_STATS (1 << 21)
#define CGEM_DESIGN_CFG1_NO_SCAN_PINS (1 << 20)
#define CGEM_DESIGN_CFG1_USER_IN_WIDTH_MASK (0x1f << 15)
#define CGEM_DESIGN_CFG1_USER_OUT_WIDTH_MASK (0x1f << 10)
#define CGEM_DESIGN_CFG1_USER_IO (1 << 9)
#define CGEM_DESIGN_CFG1_APB_REV2 (1 << 8)
#define CGEM_DESIGN_CFG1_APB_REV1 (1 << 7)
#define CGEM_DESIGN_CFG1_EXT_FIFO_INTERFACE (1 << 6)
#define CGEM_DESIGN_CFG1_NO_INT_LOOPBACK (1 << 5)
#define CGEM_DESIGN_CFG1_INT_LOOPBACK (1 << 4)
#define CGEM_DESIGN_CFG1_TDC_50 (1 << 3)
#define CGEM_DESIGN_CFG1_RDC_50 (1 << 2)
#define CGEM_DESIGN_CFG1_SERDES (1 << 1)
#define CGEM_DESIGN_CFG1_NO_PCS (1 << 0)
#define CGEM_DESIGN_CFG2 0x284 /* Design Configuration 2 */ #define CGEM_DESIGN_CFG2 0x284 /* Design Configuration 2 */
#define CGEM_DESIGN_CFG2_TX_PBUF_ADDR_SHIFT 26 #define CGEM_DESIGN_CFG2_TX_PBUF_ADDR_SHIFT 26
#define CGEM_DESIGN_CFG2_TX_PBUF_ADDR_MASK (0xf << 26) #define CGEM_DESIGN_CFG2_TX_PBUF_ADDR_MASK (0xf << 26)
#define CGEM_DESIGN_CFG2_RX_PBUF_ADDR_SHIFT 22 #define CGEM_DESIGN_CFG2_RX_PBUF_ADDR_SHIFT 22
#define CGEM_DESIGN_CFG2_RX_PBUF_ADDR_MASK (0xf << 22) #define CGEM_DESIGN_CFG2_RX_PBUF_ADDR_MASK (0xf << 22)
#define CGEM_DESIGN_CFG2_TX_PKT_BUF (1 << 21) #define CGEM_DESIGN_CFG2_TX_PKT_BUF (1 << 21)
#define CGEM_DESIGN_CFG2_RX_PKT_BUF (1 << 20) #define CGEM_DESIGN_CFG2_RX_PKT_BUF (1 << 20)
#define CGEM_DESIGN_CFG2_HPROT_VAL_SHIFT 16 #define CGEM_DESIGN_CFG2_HPROT_VAL_SHIFT 16
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#define CGEM_DESIGN_CFG5_DMA_BUS_WIDTH_SHIFT 10 #define CGEM_DESIGN_CFG5_DMA_BUS_WIDTH_SHIFT 10
#define CGEM_DESIGN_CFG5_DMA_BUS_WIDTH_MASK (3 << 10) #define CGEM_DESIGN_CFG5_DMA_BUS_WIDTH_MASK (3 << 10)
#define CGEM_DESIGN_CFG5_PHY_IDENT (1 << 9) #define CGEM_DESIGN_CFG5_PHY_IDENT (1 << 9)
#define CGEM_DESIGN_CFG5_TSU (1 << 8) #define CGEM_DESIGN_CFG5_TSU (1 << 8)
#define CGEM_DESIGN_CFG5_TX_FIFO_CNT_WIDTH_SHIFT 4 #define CGEM_DESIGN_CFG5_TX_FIFO_CNT_WIDTH_SHIFT 4
#define CGEM_DESIGN_CFG5_TX_FIFO_CNT_WIDTH_MASK (0xf << 4) #define CGEM_DESIGN_CFG5_TX_FIFO_CNT_WIDTH_MASK (0xf << 4)
#define CGEM_DESIGN_CFG5_RX_FIFO_CNT_WIDTH_MASK 0xf #define CGEM_DESIGN_CFG5_RX_FIFO_CNT_WIDTH_MASK 0xf
/* Transmit Descriptors */ #define CGEM_DESIGN_CFG6 0x294 /* Design Configuration 6 */
struct cgem_tx_desc { #define CGEM_DESIGN_CFG6_ADDR_64B (1 << 23) /* 64-bit addr cap */
uint32_t addr; #define CGEM_DESIGN_CFG6_DMA_PRIO_Q_MASK 0xfffe
uint32_t ctl; #define CGEM_DESIGN_CFG6_DMA_PRIO_Q(n) (1 << (n))
#define CGEM_TX_QN_BAR(n) (0x440 + ((n) - 1) * 4)
#define CGEM_RX_QN_BAR(n) (0x480 + ((n) - 1) * 4)
#define CGEM_TX_QBAR_HI 0x4C8
#define CGEM_RX_QBAR_HI 0x4D4
/* Transmit Descriptors: two or four 32-bit words:
* word0: address
* word1: length and control
* word2: address upper 32-bits (64-bit mode)
* word3: unused (64-bit mode)
*/
/* Tx descriptor length and control word bits: */
#define CGEM_TXDESC_USED (1U << 31) /* done txmitting */ #define CGEM_TXDESC_USED (1U << 31) /* done txmitting */
#define CGEM_TXDESC_WRAP (1 << 30) /* end descr ring */ #define CGEM_TXDESC_WRAP (1 << 30) /* end descr ring */
#define CGEM_TXDESC_RETRY_ERR (1 << 29) #define CGEM_TXDESC_RETRY_ERR (1 << 29)
#define CGEM_TXDESC_AHB_ERR (1 << 27) #define CGEM_TXDESC_AHB_ERR (1 << 27)
#define CGEM_TXDESC_LATE_COLL (1 << 26) #define CGEM_TXDESC_LATE_COLL (1 << 26)
#define CGEM_TXDESC_CKSUM_GEN_STAT_MASK (7 << 20) #define CGEM_TXDESC_CKSUM_GEN_STAT_MASK (7 << 20)
#define CGEM_TXDESC_CKSUM_GEN_STAT_VLAN_HDR_ERR (1 << 20) #define CGEM_TXDESC_CKSUM_GEN_STAT_VLAN_HDR_ERR (1 << 20)
#define CGEM_TXDESC_CKSUM_GEN_STAT_SNAP_HDR_ERR (2 << 20) #define CGEM_TXDESC_CKSUM_GEN_STAT_SNAP_HDR_ERR (2 << 20)
#define CGEM_TXDESC_CKSUM_GEN_STAT_IP_HDR_ERR (3 << 20) #define CGEM_TXDESC_CKSUM_GEN_STAT_IP_HDR_ERR (3 << 20)
#define CGEM_TXDESC_CKSUM_GEN_STAT_UNKNOWN_TYPE (4 << 20) #define CGEM_TXDESC_CKSUM_GEN_STAT_UNKNOWN_TYPE (4 << 20)
#define CGEM_TXDESC_CKSUM_GEN_STAT_UNSUPP_FRAG (5 << 20) #define CGEM_TXDESC_CKSUM_GEN_STAT_UNSUPP_FRAG (5 << 20)
#define CGEM_TXDESC_CKSUM_GEN_STAT_NOT_TCPUDP (6 << 20) #define CGEM_TXDESC_CKSUM_GEN_STAT_NOT_TCPUDP (6 << 20)
#define CGEM_TXDESC_CKSUM_GEN_STAT_SHORT_PKT (7 << 20) #define CGEM_TXDESC_CKSUM_GEN_STAT_SHORT_PKT (7 << 20)
#define CGEM_TXDESC_NO_CRC_APPENDED (1 << 16) #define CGEM_TXDESC_NO_CRC_APPENDED (1 << 16)
#define CGEM_TXDESC_LAST_BUF (1 << 15) /* last in frame */ #define CGEM_TXDESC_LAST_BUF (1 << 15) /* last in frame */
#define CGEM_TXDESC_LENGTH_MASK 0x3fff #define CGEM_TXDESC_LENGTH_MASK 0x3fff
};
struct cgem_rx_desc { /* Receive Descriptors: two or four 32-bit words:
uint32_t addr; * word0: address | WRAP and OWN flags
* word1: length and control
* word2: address upper 32 bits (64-bit mode)
* word3: unused
*/
/* address word flags: */
#define CGEM_RXDESC_WRAP (1 << 1) /* goes in addr! */ #define CGEM_RXDESC_WRAP (1 << 1) /* goes in addr! */
#define CGEM_RXDESC_OWN (1 << 0) /* buf filled */ #define CGEM_RXDESC_OWN (1 << 0) /* buf filled */
uint32_t ctl; /* length and control word flags: */
#define CGEM_RXDESC_BCAST (1U << 31)/* all 1's bcast */ #define CGEM_RXDESC_BCAST (1U << 31)/* all 1's bcast */
#define CGEM_RXDESC_MULTI_MATCH (1 << 30) /* mutlicast match */ #define CGEM_RXDESC_MULTI_MATCH (1 << 30) /* mutlicast match */
#define CGEM_RXDESC_UNICAST_MATCH (1 << 29) #define CGEM_RXDESC_UNICAST_MATCH (1 << 29)
#define CGEM_RXDESC_EXTERNAL_MATCH (1 << 28) /* ext addr match */ #define CGEM_RXDESC_EXTERNAL_MATCH (1 << 28) /* ext addr match */
#define CGEM_RXDESC_SPEC_MATCH_SHIFT 25 #define CGEM_RXDESC_SPEC_MATCH_SHIFT 25
#define CGEM_RXDESC_SPEC_MATCH_MASK (3 << 25) #define CGEM_RXDESC_SPEC_MATCH_MASK (3 << 25)
#define CGEM_RXDESC_TYPE_ID_MATCH_SHIFT 22 #define CGEM_RXDESC_TYPE_ID_MATCH_SHIFT 22
#define CGEM_RXDESC_TYPE_ID_MATCH_MASK (3 << 22) #define CGEM_RXDESC_TYPE_ID_MATCH_MASK (3 << 22)
#define CGEM_RXDESC_CKSUM_STAT_MASK (3 << 22) /* same as above */ #define CGEM_RXDESC_CKSUM_STAT_MASK (3 << 22) /* same as above */
#define CGEM_RXDESC_CKSUM_STAT_NONE (0 << 22) #define CGEM_RXDESC_CKSUM_STAT_NONE (0 << 22)
#define CGEM_RXDESC_CKSUM_STAT_IP_GOOD (1 << 22) #define CGEM_RXDESC_CKSUM_STAT_IP_GOOD (1 << 22)
#define CGEM_RXDESC_CKSUM_STAT_TCP_GOOD (2 << 22) /* and ip good */ #define CGEM_RXDESC_CKSUM_STAT_TCP_GOOD (2 << 22) /* and ip good */
#define CGEM_RXDESC_CKSUM_STAT_UDP_GOOD (3 << 22) /* and ip good */ #define CGEM_RXDESC_CKSUM_STAT_UDP_GOOD (3 << 22) /* and ip good */
#define CGEM_RXDESC_VLAN_DETECTED (1 << 21) #define CGEM_RXDESC_VLAN_DETECTED (1 << 21)
#define CGEM_RXDESC_PRIO_DETECTED (1 << 20) #define CGEM_RXDESC_PRIO_DETECTED (1 << 20)
#define CGEM_RXDESC_VLAN_PRIO_SHIFT 17 #define CGEM_RXDESC_VLAN_PRIO_SHIFT 17
#define CGEM_RXDESC_VLAN_PRIO_MASK (7 << 17) #define CGEM_RXDESC_VLAN_PRIO_MASK (7 << 17)
#define CGEM_RXDESC_CFI (1 << 16) #define CGEM_RXDESC_CFI (1 << 16)
#define CGEM_RXDESC_EOF (1 << 15) /* end of frame */ #define CGEM_RXDESC_EOF (1 << 15) /* end of frame */
#define CGEM_RXDESC_SOF (1 << 14) /* start of frame */ #define CGEM_RXDESC_SOF (1 << 14) /* start of frame */
#define CGEM_RXDESC_BAD_FCS (1 << 13) #define CGEM_RXDESC_BAD_FCS (1 << 13)
#define CGEM_RXDESC_LENGTH_MASK 0x1fff #define CGEM_RXDESC_LENGTH_MASK 0x1fff
};
#endif /* _IF_CGEM_HW_H_ */ #endif /* _IF_CGEM_HW_H_ */