Page MenuHomeFreeBSD
Differential D23718 Diff 70084 head/sys/arm/xilinx/zy7_devcfg.c

Changeset View

Standalone View

View Options

head/sys/arm/xilinx/zy7_devcfg.c

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines#define DEVCFG_SC_LOCK_INIT(sc) \
mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \ mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
"zy7_devcfg", MTX_DEF) "zy7_devcfg", MTX_DEF)
#define DEVCFG_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx); #define DEVCFG_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx);
#define DEVCFG_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED); #define DEVCFG_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED);
#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
SYSCTL_NODE(_hw, OID_AUTO, fpga, CTLFLAG_RD, 0, \ SYSCTL_NODE(_hw, OID_AUTO, fpga, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
"Xilinx Zynq-7000 PL (FPGA) section"); "Xilinx Zynq-7000 PL (FPGA) section");
static int zy7_devcfg_sysctl_pl_done(SYSCTL_HANDLER_ARGS); static int zy7_devcfg_sysctl_pl_done(SYSCTL_HANDLER_ARGS);
SYSCTL_PROC(_hw_fpga, OID_AUTO, pl_done, CTLTYPE_INT | CTLFLAG_RD, NULL, 0, SYSCTL_PROC(_hw_fpga, OID_AUTO, pl_done,
zy7_devcfg_sysctl_pl_done, "I", "PL section config DONE signal"); CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, NULL, 0,
zy7_devcfg_sysctl_pl_done, "I",
"PL section config DONE signal");
static int zy7_en_level_shifters = 1; static int zy7_en_level_shifters = 1;
SYSCTL_INT(_hw_fpga, OID_AUTO, en_level_shifters, CTLFLAG_RW, SYSCTL_INT(_hw_fpga, OID_AUTO, en_level_shifters, CTLFLAG_RW,
&zy7_en_level_shifters, 0, &zy7_en_level_shifters, 0,
"Enable PS-PL level shifters after device config"); "Enable PS-PL level shifters after device config");
static int zy7_ps_vers = 0; static int zy7_ps_vers = 0;
SYSCTL_INT(_hw, OID_AUTO, ps_vers, CTLFLAG_RD, &zy7_ps_vers, 0, SYSCTL_INT(_hw, OID_AUTO, ps_vers, CTLFLAG_RD, &zy7_ps_vers, 0,
"Zynq-7000 PS version"); "Zynq-7000 PS version");
static int zy7_devcfg_fclk_sysctl_level_shifters(SYSCTL_HANDLER_ARGS); static int zy7_devcfg_fclk_sysctl_level_shifters(SYSCTL_HANDLER_ARGS);
SYSCTL_PROC(_hw_fpga, OID_AUTO, level_shifters, SYSCTL_PROC(_hw_fpga, OID_AUTO, level_shifters,
CTLFLAG_RW | CTLTYPE_INT, CTLFLAG_RW | CTLTYPE_INT | CTLFLAG_NEEDGIANT, NULL, 0,
NULL, 0, zy7_devcfg_fclk_sysctl_level_shifters, zy7_devcfg_fclk_sysctl_level_shifters, "I",
"I", "Enable/disable level shifters"); "Enable/disable level shifters");
/* cdev entry points. */ /* cdev entry points. */
static int zy7_devcfg_open(struct cdev *, int, int, struct thread *); static int zy7_devcfg_open(struct cdev *, int, int, struct thread *);
static int zy7_devcfg_write(struct cdev *, struct uio *, int); static int zy7_devcfg_write(struct cdev *, struct uio *, int);
static int zy7_devcfg_close(struct cdev *, int, int, struct thread *); static int zy7_devcfg_close(struct cdev *, int, int, struct thread *);
struct cdevsw zy7_devcfg_cdevsw = { struct cdevsw zy7_devcfg_cdevsw = {
.d_version = D_VERSION, .d_version = D_VERSION,
▲ Show 20 Lines • Show All 222 Lines • ▼ Show 20 Lines
{ {
struct sysctl_oid *fclk_node; struct sysctl_oid *fclk_node;
char fclk_num[4]; char fclk_num[4];
int i; int i;
sysctl_ctx_init(&sc->sysctl_tree); sysctl_ctx_init(&sc->sysctl_tree);
sc->sysctl_tree_top = SYSCTL_ADD_NODE(&sc->sysctl_tree, sc->sysctl_tree_top = SYSCTL_ADD_NODE(&sc->sysctl_tree,
SYSCTL_STATIC_CHILDREN(_hw_fpga), OID_AUTO, "fclk", SYSCTL_STATIC_CHILDREN(_hw_fpga), OID_AUTO, "fclk",
CTLFLAG_RD, 0, ""); CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "");
if (sc->sysctl_tree_top == NULL) { if (sc->sysctl_tree_top == NULL) {
sysctl_ctx_free(&sc->sysctl_tree); sysctl_ctx_free(&sc->sysctl_tree);
return (-1); return (-1);
} }
for (i = 0; i < FCLK_NUM; i++) { for (i = 0; i < FCLK_NUM; i++) {
snprintf(fclk_num, sizeof(fclk_num), "%d", i); snprintf(fclk_num, sizeof(fclk_num), "%d", i);
fclk_node = SYSCTL_ADD_NODE(&sc->sysctl_tree, fclk_node = SYSCTL_ADD_NODE(&sc->sysctl_tree,
SYSCTL_CHILDREN(sc->sysctl_tree_top), OID_AUTO, fclk_num, SYSCTL_CHILDREN(sc->sysctl_tree_top), OID_AUTO, fclk_num,
CTLFLAG_RD, 0, ""); CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "");
SYSCTL_ADD_INT(&sc->sysctl_tree, SYSCTL_ADD_INT(&sc->sysctl_tree,
SYSCTL_CHILDREN(fclk_node), OID_AUTO, SYSCTL_CHILDREN(fclk_node), OID_AUTO,
"actual_freq", CTLFLAG_RD, "actual_freq", CTLFLAG_RD,
&fclk_configs[i].actual_frequency, i, &fclk_configs[i].actual_frequency, i,
"Actual frequency"); "Actual frequency");
SYSCTL_ADD_PROC(&sc->sysctl_tree, SYSCTL_ADD_PROC(&sc->sysctl_tree,
SYSCTL_CHILDREN(fclk_node), OID_AUTO, SYSCTL_CHILDREN(fclk_node), OID_AUTO,
"freq", CTLFLAG_RW | CTLTYPE_INT, "freq", CTLFLAG_RW | CTLTYPE_INT | CTLFLAG_NEEDGIANT,
&fclk_configs[i], i, &fclk_configs[i], i,
zy7_devcfg_fclk_sysctl_freq, zy7_devcfg_fclk_sysctl_freq,
"I", "Configured frequency"); "I", "Configured frequency");
SYSCTL_ADD_PROC(&sc->sysctl_tree, SYSCTL_ADD_PROC(&sc->sysctl_tree,
SYSCTL_CHILDREN(fclk_node), OID_AUTO, SYSCTL_CHILDREN(fclk_node), OID_AUTO,
"source", CTLFLAG_RW | CTLTYPE_STRING, "source", CTLFLAG_RW | CTLTYPE_STRING | CTLFLAG_NEEDGIANT,
&fclk_configs[i], i, &fclk_configs[i], i,
zy7_devcfg_fclk_sysctl_source, zy7_devcfg_fclk_sysctl_source,
"A", "Clock source"); "A", "Clock source");
} }
return (0); return (0);
} }
▲ Show 20 Lines • Show All 452 Lines • Show Last 20 Lines