Differential D23731 Diff 69960 sys/powerpc/aim/aim_machdep.c

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sys/powerpc/aim/aim_machdep.c

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	cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz)			cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz)
	{			{
	#ifdef __powerpc64__			#ifdef __powerpc64__
	/* Copy the SLB contents from the current CPU */			/* Copy the SLB contents from the current CPU */
	memcpy(pcpu->pc_aim.slb, PCPU_GET(aim.slb), sizeof(pcpu->pc_aim.slb));			memcpy(pcpu->pc_aim.slb, PCPU_GET(aim.slb), sizeof(pcpu->pc_aim.slb));
	#endif			#endif
	}			}

				/* Return 0 on handled success, otherwise signal number. */
				int
				cpu_machine_check(struct thread td, struct trapframe frame, int *ucode)
				{
				/* Check if the important information is in DSISR */
				if ((frame->srr1 & SRR1_MCHK_DATA) != 0) {
				printf("Machine check, DSISR: %016lx\n", frame->cpu.aim.dsisr);
				/* SLB multi-hit is recoverable. */
				if ((frame->cpu.aim.dsisr & DSISR_MC_SLB_MULTIHIT) != 0)
				return (0);
				/* TODO: Add other machine check recovery procedures. */
				} else {
				bdragonUnsubmitted Not Done Inline Actions Should this have a : "memory"? bdragon: Should this have a : "memory"?
				jhibbitsAuthorUnsubmitted Done Inline Actions Maybe. This is an obviously incomplete flush, anyway. The correct thing to do here is to flush the full TLB, not just the one entry. jhibbits: Maybe. This is an obviously incomplete flush, anyway. The correct thing to do here is to…
				if ((frame->srr1 & SRR1_MCHK_IFETCH_M) == SRR1_MCHK_IFETCH_SLBMH)
				return (0);
				}
				*ucode = BUS_OBJERR;
				return (SIGBUS);
				}


	#ifndef __powerpc64__			#ifndef __powerpc64__
	uint64_t			uint64_t
	va_to_vsid(pmap_t pm, vm_offset_t va)			va_to_vsid(pmap_t pm, vm_offset_t va)
	{			{
	return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK);			return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK);
	}			}

	#endif			#endif
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