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sys/arm64/arm64/locore.S
Show First 20 Lines • Show All 471 Lines • ▼ Show 20 Lines | common: | ||||
/* Link the DMAP tables */ | /* Link the DMAP tables */ | ||||
ldr x8, =DMAP_MIN_ADDRESS | ldr x8, =DMAP_MIN_ADDRESS | ||||
adr x9, pagetable_dmap; | adr x9, pagetable_dmap; | ||||
mov x10, #DMAP_TABLES | mov x10, #DMAP_TABLES | ||||
bl link_l0_pagetable | bl link_l0_pagetable | ||||
/* | /* | ||||
* Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_nG. | * Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_S1_nG. | ||||
* They are only needed early on, so the VA = PA map is uncached. | * They are only needed early on, so the VA = PA map is uncached. | ||||
*/ | */ | ||||
add x27, x24, #PAGE_SIZE | add x27, x24, #PAGE_SIZE | ||||
mov x6, x27 /* The initial page table */ | mov x6, x27 /* The initial page table */ | ||||
#if defined(SOCDEV_PA) && defined(SOCDEV_VA) | #if defined(SOCDEV_PA) && defined(SOCDEV_VA) | ||||
/* Create a table for the UART */ | /* Create a table for the UART */ | ||||
mov x7, #(ATTR_nG | ATTR_IDX(VM_MEMATTR_DEVICE)) | mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_DEVICE)) | ||||
mov x8, #(SOCDEV_VA) /* VA start */ | mov x8, #(SOCDEV_VA) /* VA start */ | ||||
mov x9, #(SOCDEV_PA) /* PA start */ | mov x9, #(SOCDEV_PA) /* PA start */ | ||||
mov x10, #1 | mov x10, #1 | ||||
bl build_l1_block_pagetable | bl build_l1_block_pagetable | ||||
#endif | #endif | ||||
#if defined(LINUX_BOOT_ABI) | #if defined(LINUX_BOOT_ABI) | ||||
/* Map FDT data ? */ | /* Map FDT data ? */ | ||||
cbz x19, 1f | cbz x19, 1f | ||||
/* Create the identity mapping for FDT data (2 MiB max) */ | /* Create the identity mapping for FDT data (2 MiB max) */ | ||||
mov x7, #(ATTR_nG | ATTR_IDX(VM_MEMATTR_UNCACHEABLE)) | mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE)) | ||||
mov x9, x0 | mov x9, x0 | ||||
mov x8, x0 /* VA start (== PA start) */ | mov x8, x0 /* VA start (== PA start) */ | ||||
mov x10, #1 | mov x10, #1 | ||||
bl build_l1_block_pagetable | bl build_l1_block_pagetable | ||||
1: | 1: | ||||
#endif | #endif | ||||
/* Create the VA = PA map */ | /* Create the VA = PA map */ | ||||
mov x7, #(ATTR_nG | ATTR_IDX(VM_MEMATTR_UNCACHEABLE)) | mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE)) | ||||
mov x9, x27 | mov x9, x27 | ||||
mov x8, x9 /* VA start (== PA start) */ | mov x8, x9 /* VA start (== PA start) */ | ||||
mov x10, #1 | mov x10, #1 | ||||
bl build_l1_block_pagetable | bl build_l1_block_pagetable | ||||
/* Move to the l0 table */ | /* Move to the l0 table */ | ||||
add x27, x27, #PAGE_SIZE | add x27, x27, #PAGE_SIZE | ||||
▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines | build_l2_block_pagetable: | ||||
/* Find the table index */ | /* Find the table index */ | ||||
lsr x11, x8, #L2_SHIFT | lsr x11, x8, #L2_SHIFT | ||||
and x11, x11, #Ln_ADDR_MASK | and x11, x11, #Ln_ADDR_MASK | ||||
/* Build the L2 block entry */ | /* Build the L2 block entry */ | ||||
lsl x12, x7, #2 | lsl x12, x7, #2 | ||||
orr x12, x12, #L2_BLOCK | orr x12, x12, #L2_BLOCK | ||||
orr x12, x12, #(ATTR_AF) | orr x12, x12, #(ATTR_AF) | ||||
orr x12, x12, #(ATTR_UXN) | orr x12, x12, #(ATTR_S1_UXN) | ||||
#ifdef SMP | #ifdef SMP | ||||
orr x12, x12, ATTR_SH(ATTR_SH_IS) | orr x12, x12, ATTR_SH(ATTR_SH_IS) | ||||
#endif | #endif | ||||
/* Only use the output address bits */ | /* Only use the output address bits */ | ||||
lsr x9, x9, #L2_SHIFT | lsr x9, x9, #L2_SHIFT | ||||
/* Set the physical address for this virtual address */ | /* Set the physical address for this virtual address */ | ||||
▲ Show 20 Lines • Show All 190 Lines • Show Last 20 Lines |