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sys/dev/xl/if_xl.c
Show First 20 Lines • Show All 1,973 Lines • ▼ Show 20 Lines | |||||
*/ | */ | ||||
static void | static void | ||||
xl_rxeof_task(void *arg, int pending) | xl_rxeof_task(void *arg, int pending) | ||||
{ | { | ||||
struct xl_softc *sc = (struct xl_softc *)arg; | struct xl_softc *sc = (struct xl_softc *)arg; | ||||
XL_LOCK(sc); | XL_LOCK(sc); | ||||
if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING) | if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING) | ||||
xl_rxeof(sc); | NET_EPOCH_WRAP(xl_rxeof, (sc)); | ||||
XL_UNLOCK(sc); | XL_UNLOCK(sc); | ||||
} | } | ||||
/* | /* | ||||
* A frame was downloaded to the chip. It's safe for us to clean up | * A frame was downloaded to the chip. It's safe for us to clean up | ||||
* the list buffers. | * the list buffers. | ||||
*/ | */ | ||||
static void | static void | ||||
▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Lines | "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); | ||||
*/ | */ | ||||
CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); | CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); | ||||
} | } | ||||
} | } | ||||
static void | static void | ||||
xl_intr(void *arg) | xl_intr(void *arg) | ||||
{ | { | ||||
struct epoch_tracker et; | |||||
struct xl_softc *sc = arg; | struct xl_softc *sc = arg; | ||||
struct ifnet *ifp = sc->xl_ifp; | struct ifnet *ifp = sc->xl_ifp; | ||||
u_int16_t status; | u_int16_t status; | ||||
XL_LOCK(sc); | XL_LOCK(sc); | ||||
#ifdef DEVICE_POLLING | #ifdef DEVICE_POLLING | ||||
if (ifp->if_capenable & IFCAP_POLLING) { | if (ifp->if_capenable & IFCAP_POLLING) { | ||||
XL_UNLOCK(sc); | XL_UNLOCK(sc); | ||||
return; | return; | ||||
} | } | ||||
#endif | #endif | ||||
for (;;) { | for (;;) { | ||||
status = CSR_READ_2(sc, XL_STATUS); | status = CSR_READ_2(sc, XL_STATUS); | ||||
if ((status & XL_INTRS) == 0 || status == 0xFFFF) | if ((status & XL_INTRS) == 0 || status == 0xFFFF) | ||||
break; | break; | ||||
CSR_WRITE_2(sc, XL_COMMAND, | CSR_WRITE_2(sc, XL_COMMAND, | ||||
XL_CMD_INTR_ACK|(status & XL_INTRS)); | XL_CMD_INTR_ACK|(status & XL_INTRS)); | ||||
if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) | if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) | ||||
break; | break; | ||||
if (status & XL_STAT_UP_COMPLETE) { | if (status & XL_STAT_UP_COMPLETE) { | ||||
NET_EPOCH_ENTER(et); | |||||
if (xl_rxeof(sc) == 0) { | if (xl_rxeof(sc) == 0) { | ||||
while (xl_rx_resync(sc)) | while (xl_rx_resync(sc)) | ||||
xl_rxeof(sc); | xl_rxeof(sc); | ||||
} | } | ||||
NET_EPOCH_EXIT(et); | |||||
} | } | ||||
if (status & XL_STAT_DOWN_COMPLETE) { | if (status & XL_STAT_DOWN_COMPLETE) { | ||||
if (sc->xl_type == XL_TYPE_905B) | if (sc->xl_type == XL_TYPE_905B) | ||||
xl_txeof_90xB(sc); | xl_txeof_90xB(sc); | ||||
else | else | ||||
xl_txeof(sc); | xl_txeof(sc); | ||||
} | } | ||||
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xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) | xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) | ||||
{ | { | ||||
struct xl_softc *sc = ifp->if_softc; | struct xl_softc *sc = ifp->if_softc; | ||||
int rx_npkts; | int rx_npkts; | ||||
XL_LOCK_ASSERT(sc); | XL_LOCK_ASSERT(sc); | ||||
sc->rxcycles = count; | sc->rxcycles = count; | ||||
rx_npkts = xl_rxeof(sc); | rx_npkts = NET_EPOCH_WRAP_RET(xl_rxeof, (sc)); | ||||
if (sc->xl_type == XL_TYPE_905B) | if (sc->xl_type == XL_TYPE_905B) | ||||
xl_txeof_90xB(sc); | xl_txeof_90xB(sc); | ||||
else | else | ||||
xl_txeof(sc); | xl_txeof(sc); | ||||
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { | if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { | ||||
if (sc->xl_type == XL_TYPE_905B) | if (sc->xl_type == XL_TYPE_905B) | ||||
xl_start_90xB_locked(ifp); | xl_start_90xB_locked(ifp); | ||||
▲ Show 20 Lines • Show All 846 Lines • ▼ Show 20 Lines | #endif /* DEVICE_POLLING */ | ||||
} | } | ||||
return (error); | return (error); | ||||
} | } | ||||
static int | static int | ||||
xl_watchdog(struct xl_softc *sc) | xl_watchdog(struct xl_softc *sc) | ||||
{ | { | ||||
struct epoch_tracker et; | |||||
struct ifnet *ifp = sc->xl_ifp; | struct ifnet *ifp = sc->xl_ifp; | ||||
u_int16_t status = 0; | u_int16_t status = 0; | ||||
int misintr; | int misintr; | ||||
XL_LOCK_ASSERT(sc); | XL_LOCK_ASSERT(sc); | ||||
if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0) | if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0) | ||||
return (0); | return (0); | ||||
NET_EPOCH_ENTER(et); | |||||
xl_rxeof(sc); | xl_rxeof(sc); | ||||
NET_EPOCH_EXIT(et); | |||||
xl_txeoc(sc); | xl_txeoc(sc); | ||||
misintr = 0; | misintr = 0; | ||||
if (sc->xl_type == XL_TYPE_905B) { | if (sc->xl_type == XL_TYPE_905B) { | ||||
xl_txeof_90xB(sc); | xl_txeof_90xB(sc); | ||||
if (sc->xl_cdata.xl_tx_cnt == 0) | if (sc->xl_cdata.xl_tx_cnt == 0) | ||||
misintr++; | misintr++; | ||||
} else { | } else { | ||||
xl_txeof(sc); | xl_txeof(sc); | ||||
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