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sys/dev/ffec/if_ffec.c
Show First 20 Lines • Show All 1,295 Lines • ▼ Show 20 Lines | ffec_intr(void *arg) | ||||
if (ier & FEC_IER_TXF) { | if (ier & FEC_IER_TXF) { | ||||
WR4(sc, FEC_IER_REG, FEC_IER_TXF); | WR4(sc, FEC_IER_REG, FEC_IER_TXF); | ||||
ffec_txfinish_locked(sc); | ffec_txfinish_locked(sc); | ||||
} | } | ||||
if (ier & FEC_IER_RXF) { | if (ier & FEC_IER_RXF) { | ||||
WR4(sc, FEC_IER_REG, FEC_IER_RXF); | WR4(sc, FEC_IER_REG, FEC_IER_RXF); | ||||
ffec_rxfinish_locked(sc); | NET_EPOCH_WRAP(ffec_rxfinish_locked, (sc)); | ||||
} | } | ||||
/* | /* | ||||
* We actually don't care about most errors, because the hardware copes | * We actually don't care about most errors, because the hardware copes | ||||
* with them just fine, discarding the incoming bad frame, or forcing a | * with them just fine, discarding the incoming bad frame, or forcing a | ||||
* bad CRC onto an outgoing bad frame, and counting the errors in the | * bad CRC onto an outgoing bad frame, and counting the errors in the | ||||
* stats registers. The one that really matters is EBERR (DMA bus | * stats registers. The one that really matters is EBERR (DMA bus | ||||
* error) because the hardware automatically clears ECR[ETHEREN] and we | * error) because the hardware automatically clears ECR[ETHEREN] and we | ||||
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