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sys/powerpc/aim/trap_subr64.S
| Show First 20 Lines • Show All 312 Lines • ▼ Show 20 Lines | */ | ||||
| .p2align 3 | .p2align 3 | ||||
| CNAME(rstcode): | CNAME(rstcode): | ||||
| /* | /* | ||||
| * Check if this is software reset or | * Check if this is software reset or | ||||
| * processor is waking up from power saving mode | * processor is waking up from power saving mode | ||||
| * It is software reset when 46:47 = 0b00 | * It is software reset when 46:47 = 0b00 | ||||
| */ | */ | ||||
| /* 0x00 */ | /* 0x00 */ | ||||
| ld %r2,TRAP_GENTRAP(0) /* Real-mode &generictrap */ | ld %r2,TRAP_ENTRY(0) /* Real-mode &generictrap */ | ||||
| mfsrr1 %r9 /* Load SRR1 into r9 */ | mfsrr1 %r9 /* Load SRR1 into r9 */ | ||||
| andis. %r9,%r9,0x3 /* Logic AND with 46:47 bits */ | andis. %r9,%r9,0x3 /* Logic AND with 46:47 bits */ | ||||
| beq 2f /* Branch if software reset */ | beq 2f /* Branch if software reset */ | ||||
| /* 0x10 */ | /* 0x10 */ | ||||
| /* Reset was wakeup */ | /* Reset was wakeup */ | ||||
| addi %r9,%r2,(cpu_wakeup_handler-generictrap) | addi %r9,%r2,(cpu_wakeup_handler-generictrap) | ||||
| b 1f /* Was power save, do the wakeup */ | b 1f /* Was power save, do the wakeup */ | ||||
| ▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines | |||||
| */ | */ | ||||
| .globl CNAME(trapcode),CNAME(trapcodeend) | .globl CNAME(trapcode),CNAME(trapcodeend) | ||||
| .p2align 3 | .p2align 3 | ||||
| CNAME(trapcode): | CNAME(trapcode): | ||||
| mtsprg1 %r1 /* save SP */ | mtsprg1 %r1 /* save SP */ | ||||
| mflr %r1 /* Save the old LR in r1 */ | mflr %r1 /* Save the old LR in r1 */ | ||||
| mtsprg2 %r1 /* And then in SPRG2 */ | mtsprg2 %r1 /* And then in SPRG2 */ | ||||
| ld %r1,TRAP_GENTRAP(0) | ld %r1,TRAP_ENTRY(0) | ||||
| mtlr %r1 | mtlr %r1 | ||||
| li %r1, 0xe0 /* How to get the vector from LR */ | li %r1, 0xe0 /* How to get the vector from LR */ | ||||
| blrl /* Branch to generictrap */ | blrl /* Branch to generictrap */ | ||||
| CNAME(trapcodeend): | CNAME(trapcodeend): | ||||
| /* Same thing for traps setting HSRR0/HSRR1 */ | /* Same thing for traps setting HSRR0/HSRR1 */ | ||||
| .globl CNAME(hypertrapcode),CNAME(hypertrapcodeend) | .globl CNAME(hypertrapcode),CNAME(hypertrapcodeend) | ||||
| .p2align 3 | .p2align 3 | ||||
| Show All 30 Lines | CNAME(slbtrap): | ||||
| /* 0x20 */ | /* 0x20 */ | ||||
| /* User mode */ | /* User mode */ | ||||
| ld %r2,(PC_SLBSAVE+104)(%r1) | ld %r2,(PC_SLBSAVE+104)(%r1) | ||||
| mtcr %r2 /* restore CR */ | mtcr %r2 /* restore CR */ | ||||
| ld %r2,(PC_SLBSAVE+16)(%r1) /* restore r2 */ | ld %r2,(PC_SLBSAVE+16)(%r1) /* restore r2 */ | ||||
| mflr %r1 | mflr %r1 | ||||
| /* 0x30 */ | /* 0x30 */ | ||||
| mtsprg2 %r1 /* save LR in SPRG2 */ | mtsprg2 %r1 /* save LR in SPRG2 */ | ||||
| ld %r1,TRAP_GENTRAP(0) /* real-mode &generictrap */ | ld %r1,TRAP_ENTRY(0) /* real-mode &generictrap */ | ||||
| mtlr %r1 | mtlr %r1 | ||||
| li %r1, 0x80 /* How to get the vector from LR */ | li %r1, 0x80 /* How to get the vector from LR */ | ||||
| /* 0x40 */ | /* 0x40 */ | ||||
| blrl /* Branch to generictrap */ | blrl /* Branch to generictrap */ | ||||
| 2: mflr %r2 /* Save the old LR in r2 */ | 2: mflr %r2 /* Save the old LR in r2 */ | ||||
| /* Kernel mode */ | /* Kernel mode */ | ||||
| ld %r1,TRAP_GENTRAP(0) /* Real-mode &generictrap */ | ld %r1,TRAP_GENTRAP(0) /* Real-mode &generictrap */ | ||||
| addi %r1,%r1,(kern_slbtrap-generictrap) | addi %r1,%r1,(kern_slbtrap-generictrap) | ||||
| ▲ Show 20 Lines • Show All 445 Lines • ▼ Show 20 Lines | CNAME(dblow): | ||||
| bf 17,1f /* branch if privileged */ | bf 17,1f /* branch if privileged */ | ||||
| /* Unprivileged case */ | /* Unprivileged case */ | ||||
| mtcr %r29 /* put the condition register back */ | mtcr %r29 /* put the condition register back */ | ||||
| mfsprg2 %r29 /* ... and r29 */ | mfsprg2 %r29 /* ... and r29 */ | ||||
| mflr %r1 /* save LR */ | mflr %r1 /* save LR */ | ||||
| mtsprg2 %r1 /* And then in SPRG2 */ | mtsprg2 %r1 /* And then in SPRG2 */ | ||||
| ld %r1, TRAP_GENTRAP(0) /* Get branch address */ | ld %r1, TRAP_ENTRY(0) /* Get branch address */ | ||||
| mtlr %r1 | mtlr %r1 | ||||
| li %r1, 0 /* How to get the vector from LR */ | li %r1, 0 /* How to get the vector from LR */ | ||||
| blrl /* Branch to generictrap */ | blrl /* Branch to generictrap */ | ||||
| /* No fallthrough */ | /* No fallthrough */ | ||||
| 1: | 1: | ||||
| GET_CPUINFO(%r1) | GET_CPUINFO(%r1) | ||||
| std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r1) /* free r27 */ | std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r1) /* free r27 */ | ||||
| std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */ | std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */ | ||||
| Show All 11 Lines | |||||