Changeset View
Changeset View
Standalone View
Standalone View
sys/arm/altera/socfpga/socfpga_rstmgr.c
Show All 12 Lines | |||||
{ | { | ||||
struct sysctl_oid_list *children; | struct sysctl_oid_list *children; | ||||
struct sysctl_ctx_list *ctx; | struct sysctl_ctx_list *ctx; | ||||
ctx = device_get_sysctl_ctx(sc->dev); | ctx = device_get_sysctl_ctx(sc->dev); | ||||
children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); | children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); | ||||
SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fpga2hps", | SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fpga2hps", | ||||
CTLTYPE_UINT | CTLFLAG_RW, sc, RSTMGR_SYSCTL_FPGA2HPS, | CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, | ||||
sc, RSTMGR_SYSCTL_FPGA2HPS, | |||||
rstmgr_sysctl, "I", "Enable fpga2hps bridge"); | rstmgr_sysctl, "I", "Enable fpga2hps bridge"); | ||||
SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lwhps2fpga", | SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lwhps2fpga", | ||||
CTLTYPE_UINT | CTLFLAG_RW, sc, RSTMGR_SYSCTL_LWHPS2FPGA, | CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, | ||||
sc, RSTMGR_SYSCTL_LWHPS2FPGA, | |||||
rstmgr_sysctl, "I", "Enable lwhps2fpga bridge"); | rstmgr_sysctl, "I", "Enable lwhps2fpga bridge"); | ||||
SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hps2fpga", | SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hps2fpga", | ||||
CTLTYPE_UINT | CTLFLAG_RW, sc, RSTMGR_SYSCTL_HPS2FPGA, | CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, | ||||
sc, RSTMGR_SYSCTL_HPS2FPGA, | |||||
rstmgr_sysctl, "I", "Enable hps2fpga bridge"); | rstmgr_sysctl, "I", "Enable hps2fpga bridge"); | ||||
return (0); | return (0); | ||||
} | } | ||||
static int | static int | ||||
rstmgr_probe(device_t dev) | rstmgr_probe(device_t dev) | ||||
{ | { | ||||
Show All 12 Lines |