Changeset View
Changeset View
Standalone View
Standalone View
sys/arm/ti/aintc.c
Show All 39 Lines | |||||
#include <machine/bus.h> | #include <machine/bus.h> | ||||
#include <machine/intr.h> | #include <machine/intr.h> | ||||
#include <dev/fdt/fdt_common.h> | #include <dev/fdt/fdt_common.h> | ||||
#include <dev/ofw/openfirm.h> | #include <dev/ofw/openfirm.h> | ||||
#include <dev/ofw/ofw_bus.h> | #include <dev/ofw/ofw_bus.h> | ||||
#include <dev/ofw/ofw_bus_subr.h> | #include <dev/ofw/ofw_bus_subr.h> | ||||
#include "pic_if.h" | |||||
#define INTC_REVISION 0x00 | #define INTC_REVISION 0x00 | ||||
#define INTC_SYSCONFIG 0x10 | #define INTC_SYSCONFIG 0x10 | ||||
#define INTC_SYSSTATUS 0x14 | #define INTC_SYSSTATUS 0x14 | ||||
#define INTC_SIR_IRQ 0x40 | #define INTC_SIR_IRQ 0x40 | ||||
#define INTC_CONTROL 0x48 | #define INTC_CONTROL 0x48 | ||||
#define INTC_THRESHOLD 0x68 | #define INTC_THRESHOLD 0x68 | ||||
#define INTC_MIR_CLEAR(x) (0x88 + ((x) * 0x20)) | #define INTC_MIR_CLEAR(x) (0x88 + ((x) * 0x20)) | ||||
#define INTC_MIR_SET(x) (0x8C + ((x) * 0x20)) | #define INTC_MIR_SET(x) (0x8C + ((x) * 0x20)) | ||||
#define INTC_ISR_SET(x) (0x90 + ((x) * 0x20)) | #define INTC_ISR_SET(x) (0x90 + ((x) * 0x20)) | ||||
#define INTC_ISR_CLEAR(x) (0x94 + ((x) * 0x20)) | #define INTC_ISR_CLEAR(x) (0x94 + ((x) * 0x20)) | ||||
struct ti_aintc_softc { | struct ti_aintc_softc { | ||||
device_t sc_dev; | device_t sc_dev; | ||||
struct resource * aintc_res[3]; | struct resource * aintc_res[3]; | ||||
bus_space_tag_t aintc_bst; | bus_space_tag_t aintc_bst; | ||||
bus_space_handle_t aintc_bsh; | bus_space_handle_t aintc_bsh; | ||||
void * aintc_intrhand; | |||||
uint8_t ver; | uint8_t ver; | ||||
}; | }; | ||||
static struct resource_spec ti_aintc_spec[] = { | static struct resource_spec ti_aintc_spec[] = { | ||||
{ SYS_RES_MEMORY, 0, RF_ACTIVE }, | { SYS_RES_MEMORY, 0, RF_ACTIVE }, | ||||
{ SYS_RES_IRQ, 0, RF_ACTIVE }, | |||||
{ -1, 0 } | { -1, 0 } | ||||
}; | }; | ||||
#define aintc_read_4(_sc,reg) \ | |||||
bus_space_read_4(_sc->aintc_bst, _sc->aintc_bsh, (reg)) | |||||
#define aintc_write_4(_sc, reg, val) \ | |||||
bus_space_write_4(_sc->aintc_bst, _sc->aintc_bsh, (reg), (val)) | |||||
static struct ti_aintc_softc *ti_aintc_sc = NULL; | static int ti_aintc_probe(device_t); | ||||
static int ti_aintc_attach(device_t); | |||||
static void ti_aintc_mask(device_t, int); | |||||
static void ti_aintc_unmask(device_t, int); | |||||
static void ti_aintc_eoi(device_t, int); | |||||
static int ti_aintc_intr(void *); | |||||
#define aintc_read_4(reg) \ | |||||
bus_space_read_4(ti_aintc_sc->aintc_bst, ti_aintc_sc->aintc_bsh, reg) | |||||
#define aintc_write_4(reg, val) \ | |||||
bus_space_write_4(ti_aintc_sc->aintc_bst, ti_aintc_sc->aintc_bsh, reg, val) | |||||
static int | static int | ||||
ti_aintc_probe(device_t dev) | ti_aintc_probe(device_t dev) | ||||
{ | { | ||||
if (!ofw_bus_status_okay(dev)) | |||||
return (ENXIO); | |||||
if (!ofw_bus_is_compatible(dev, "ti,aintc")) | if (!ofw_bus_is_compatible(dev, "ti,aintc")) | ||||
return (ENXIO); | return (ENXIO); | ||||
device_set_desc(dev, "TI AINTC Interrupt Controller"); | device_set_desc(dev, "TI AINTC Interrupt Controller"); | ||||
return (BUS_PROBE_DEFAULT); | return (BUS_PROBE_DEFAULT); | ||||
} | } | ||||
static int | static int | ||||
ti_aintc_attach(device_t dev) | ti_aintc_attach(device_t dev) | ||||
{ | { | ||||
struct ti_aintc_softc *sc = device_get_softc(dev); | struct ti_aintc_softc *sc = device_get_softc(dev); | ||||
uint32_t x; | uint32_t x; | ||||
sc->sc_dev = dev; | sc->sc_dev = dev; | ||||
if (ti_aintc_sc) | |||||
return (ENXIO); | |||||
if (bus_alloc_resources(dev, ti_aintc_spec, sc->aintc_res)) { | if (bus_alloc_resources(dev, ti_aintc_spec, sc->aintc_res)) { | ||||
device_printf(dev, "could not allocate resources\n"); | device_printf(dev, "could not allocate resources\n"); | ||||
return (ENXIO); | return (ENXIO); | ||||
} | } | ||||
sc->aintc_bst = rman_get_bustag(sc->aintc_res[0]); | sc->aintc_bst = rman_get_bustag(sc->aintc_res[0]); | ||||
sc->aintc_bsh = rman_get_bushandle(sc->aintc_res[0]); | sc->aintc_bsh = rman_get_bushandle(sc->aintc_res[0]); | ||||
ti_aintc_sc = sc; | arm_register_pic(dev); | ||||
x = aintc_read_4(INTC_REVISION); | if (bus_setup_intr(dev, sc->aintc_res[1], | ||||
INTR_TYPE_MISC | INTR_CONTROLLER, ti_aintc_intr, NULL, | |||||
sc, &sc->aintc_intrhand)) { | |||||
device_printf(dev, "could not install interrupt handler\n"); | |||||
return (ENXIO); | |||||
} | |||||
x = aintc_read_4(sc, INTC_REVISION); | |||||
device_printf(dev, "Revision %u.%u\n",(x >> 4) & 0xF, x & 0xF); | device_printf(dev, "Revision %u.%u\n",(x >> 4) & 0xF, x & 0xF); | ||||
/* SoftReset */ | /* SoftReset */ | ||||
aintc_write_4(INTC_SYSCONFIG, 2); | aintc_write_4(sc, INTC_SYSCONFIG, 2); | ||||
/* Wait for reset to complete */ | /* Wait for reset to complete */ | ||||
while(!(aintc_read_4(INTC_SYSSTATUS) & 1)); | while(!(aintc_read_4(sc, INTC_SYSSTATUS) & 1)); | ||||
/*Set Priority Threshold */ | /*Set Priority Threshold */ | ||||
aintc_write_4(INTC_THRESHOLD, 0xFF); | aintc_write_4(sc, INTC_THRESHOLD, 0xFF); | ||||
return (0); | return (0); | ||||
} | } | ||||
static device_method_t ti_aintc_methods[] = { | static device_method_t ti_aintc_methods[] = { | ||||
/* Device interface */ | |||||
DEVMETHOD(device_probe, ti_aintc_probe), | DEVMETHOD(device_probe, ti_aintc_probe), | ||||
DEVMETHOD(device_attach, ti_aintc_attach), | DEVMETHOD(device_attach, ti_aintc_attach), | ||||
/* PIC interface */ | |||||
DEVMETHOD(pic_mask, ti_aintc_mask), | |||||
DEVMETHOD(pic_unmask, ti_aintc_unmask), | |||||
DEVMETHOD(pic_eoi, ti_aintc_eoi), | |||||
{ 0, 0 } | { 0, 0 } | ||||
}; | }; | ||||
static driver_t ti_aintc_driver = { | static driver_t ti_aintc_driver = { | ||||
"aintc", | "aintc", | ||||
ti_aintc_methods, | ti_aintc_methods, | ||||
sizeof(struct ti_aintc_softc), | sizeof(struct ti_aintc_softc), | ||||
}; | }; | ||||
static devclass_t ti_aintc_devclass; | static devclass_t ti_aintc_devclass; | ||||
DRIVER_MODULE(aintc, simplebus, ti_aintc_driver, ti_aintc_devclass, 0, 0); | DRIVER_MODULE(aintc, simplebus, ti_aintc_driver, ti_aintc_devclass, 0, 0); | ||||
int | static int | ||||
arm_get_next_irq(int last_irq) | ti_aintc_intr(void *arg) | ||||
{ | { | ||||
struct ti_aintc_softc *sc = (struct ti_aintc_softc *)arg; | |||||
uint32_t active_irq; | uint32_t active_irq; | ||||
if (last_irq != -1) { | |||||
aintc_write_4(INTC_ISR_CLEAR(last_irq >> 5), | |||||
1UL << (last_irq & 0x1F)); | |||||
aintc_write_4(INTC_CONTROL,1); | |||||
} | |||||
/* Get the next active interrupt */ | /* Get the next active interrupt */ | ||||
active_irq = aintc_read_4(INTC_SIR_IRQ); | active_irq = aintc_read_4(sc, INTC_SIR_IRQ); | ||||
/* Check for spurious interrupt */ | /* Check for spurious interrupt */ | ||||
if ((active_irq & 0xffffff80)) { | if ((active_irq & 0xffffff80)) { | ||||
device_printf(ti_aintc_sc->sc_dev, | device_printf(sc->sc_dev, | ||||
"Spurious interrupt detected (0x%08x)\n", active_irq); | "Spurious interrupt detected (0x%08x)\n", active_irq); | ||||
aintc_write_4(INTC_SIR_IRQ, 0); | return FILTER_HANDLED; | ||||
return -1; | |||||
} | } | ||||
if (active_irq != last_irq) | arm_dispatch_irq(sc->sc_dev, NULL, active_irq); | ||||
return active_irq; | return FILTER_HANDLED; | ||||
else | |||||
return -1; | |||||
} | } | ||||
void | static void | ||||
arm_mask_irq(uintptr_t nb) | ti_aintc_mask(device_t dev, int irq) | ||||
{ | { | ||||
aintc_write_4(INTC_MIR_SET(nb >> 5), (1UL << (nb & 0x1F))); | struct ti_aintc_softc *sc = device_get_softc(dev); | ||||
aintc_write_4(sc, INTC_MIR_SET(irq >> 5), (1UL << (irq & 0x1F))); | |||||
} | } | ||||
void | static void | ||||
arm_unmask_irq(uintptr_t nb) | ti_aintc_unmask(device_t dev, int irq) | ||||
{ | { | ||||
struct ti_aintc_softc *sc = device_get_softc(dev); | |||||
aintc_write_4(sc, INTC_MIR_CLEAR(irq >> 5), (1UL << (irq & 0x1F))); | |||||
arm_irq_memory_barrier(nb); | arm_irq_memory_barrier(nb); | ||||
static void | |||||
ti_aintc_eoi(device_t dev, int irq) | |||||
{ | |||||
struct ti_aintc_softc *sc = device_get_softc(dev); | |||||
aintc_write_4(sc, INTC_ISR_CLEAR(irq >> 5), | |||||
1UL << (irq & 0x1F)); | |||||
aintc_write_4(sc, INTC_CONTROL,1); | |||||
} | |||||
aintc_write_4(INTC_MIR_CLEAR(nb >> 5), (1UL << (nb & 0x1F))); | aintc_write_4(INTC_MIR_CLEAR(nb >> 5), (1UL << (nb & 0x1F))); | ||||
} | } |