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sys/dev/drm/bridges/dw_hdmi/dw_hdmireg.h
- This file was added.
/*- | |||||
* Copyright (c) 2019 Emmanuel Vadot <manu@FreeBSD.org> | |||||
* | |||||
* Redistribution and use in source and binary forms, with or without | |||||
* modification, are permitted provided that the following conditions | |||||
* are met: | |||||
* 1. Redistributions of source code must retain the above copyright | |||||
* notice, this list of conditions and the following disclaimer. | |||||
* 2. Redistributions in binary form must reproduce the above copyright | |||||
* notice, this list of conditions and the following disclaimer in the | |||||
* documentation and/or other materials provided with the distribution. | |||||
* | |||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR | |||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | |||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. | |||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, | |||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED | |||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |||||
* SUCH DAMAGE. | |||||
* | |||||
* $FreeBSD$ | |||||
*/ | |||||
#ifndef _DW_HDMI_H_ | |||||
#define _DW_HDMI_H_ | |||||
#define DW_HDMI_DESIGN_ID 0x00 | |||||
#define DW_HDMI_REVISION_ID 0x01 | |||||
#define DW_HDMI_PRODUCT_ID0 0x02 | |||||
#define DW_HDMI_PRODUCT_ID1 0x03 | |||||
#define DW_HDMI_CONFIG0_ID 0x04 | |||||
#define DW_HDMI_CONFIG1_ID 0x05 | |||||
#define DW_HDMI_CONFIG2_ID 0x06 | |||||
#define DW_HDMI_CONFIG3_ID 0x07 | |||||
#define DW_HDMI_IH_FC_STAT0 0x0100 | |||||
#define DW_HDMI_IH_FC_STAT1 0x0101 | |||||
#define DW_HDMI_IH_FC_STAT2 0x0102 | |||||
#define DW_HDMI_IH_AS_STAT0 0x0103 | |||||
#define DW_HDMI_IH_PHY_STAT0 0x0104 | |||||
#define DW_HDMI_IH_I2CM_STAT0 0x0105 | |||||
#define DW_HDMI_IH_I2CM_STAT0_ERROR (1 << 0) | |||||
#define DW_HDMI_IH_I2CM_STAT0_DONE (1 << 1) | |||||
#define DW_HDMI_IH_CEC_STAT0 0x0106 | |||||
#define DW_HDMI_IH_VP_STAT0 0x0107 | |||||
#define DW_HDMI_IH_I2CMPHY_STAT0 0x0108 | |||||
#define DW_HDMI_IH_AHBDMAAUD_STAT0 0x0109 | |||||
#define DW_HDMI_IH_MUTE_FC_STAT0 0x0180 | |||||
#define DW_HDMI_IH_MUTE_FC_STAT1 0x0181 | |||||
#define DW_HDMI_IH_MUTE_FC_STAT2 0x0182 | |||||
#define DW_HDMI_IH_MUTE_AS_STAT0 0x0183 | |||||
#define DW_HDMI_IH_MUTE_PHY_STAT0 0x0184 | |||||
#define DW_HDMI_IH_MUTE_I2CM_STAT0 0x0185 | |||||
#define DW_HDMI_IH_MUTE_I2CM_STAT0_ERROR (1 << 0) | |||||
#define DW_HDMI_IH_MUTE_I2CM_STAT0_DONE (1 << 1) | |||||
#define DW_HDMI_IH_MUTE_CEC_STAT0 0x0186 | |||||
#define DW_HDMI_IH_MUTE_VP_STAT0 0x0187 | |||||
#define DW_HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188 | |||||
#define DW_HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189 | |||||
#define DW_HDMI_IH_MUTE 0x01FF | |||||
#define DW_HDMI_IH_MUTE_ALL (1 << 0) | |||||
#define DW_HDMI_IH_MUTE_WAKEUP (1 << 1) | |||||
/* Video Packetizer */ | |||||
#define DW_HDMI_VP_STATUS 0x0800 | |||||
#define DW_HDMI_VP_PR_CD 0x0801 | |||||
#define DW_HDMI_VP_STUFF 0x0802 | |||||
#define DW_HDMI_VP_REMAP 0x0803 | |||||
#define DW_HDMI_VP_CONF 0x0804 | |||||
#define DW_HDMI_VP_MASK 0x0807 | |||||
/* Frame Composer */ | |||||
#define DW_HDMI_FC_INVIDCONF 0x1000 | |||||
#define DW_HDMI_FC_INVIDCONF_HSYNC_POL_HIGH (1 << 5) | |||||
#define DW_HDMI_FC_INVIDCONF_VSYNC_POL_HIGH (1 << 6) | |||||
#define DW_HDMI_FC_INVIDCONF_DATA_POL_HIGH (1 << 4) | |||||
#define DW_HDMI_FC_INVIDCONF_HDMI_MODE (1 << 3) | |||||
#define DW_HDMI_FC_INVIDCONF_INTERLACED_MODE (1 << 0) | |||||
#define DW_HDMI_FC_INHACTIV0 0x1001 | |||||
#define DW_HDMI_FC_INHACTIV1 0x1002 | |||||
#define DW_HDMI_FC_INHBLANK0 0x1003 | |||||
#define DW_HDMI_FC_INHBLANK1 0x1004 | |||||
#define DW_HDMI_FC_INVACTIV0 0x1005 | |||||
#define DW_HDMI_FC_INVACTIV1 0x1006 | |||||
#define DW_HDMI_FC_INVBLANK 0x1007 | |||||
#define DW_HDMI_FC_HSYNCINDELAY0 0x1008 | |||||
#define DW_HDMI_FC_HSYNCINDELAY1 0x1009 | |||||
#define DW_HDMI_FC_HSYNCINWIDTH0 0x100A | |||||
#define DW_HDMI_FC_HSYNCINWIDTH1 0x100B | |||||
#define DW_HDMI_FC_VSYNCINDELAY 0x100C | |||||
#define DW_HDMI_FC_VSYNCINWIDTH 0x100D | |||||
#define DW_HDMI_FC_CTRLDUR 0x1011 | |||||
#define DW_HDMI_FC_EXCTRLDUR 0x1012 | |||||
#define DW_HDMI_FC_EXCTRLSPAC 0x1013 | |||||
#define DW_HDMI_FC_CH0PREAM 0x1014 | |||||
#define DW_HDMI_FC_CH1PREAM 0x1015 | |||||
#define DW_HDMI_FC_CH2PREAM 0x1016 | |||||
#define DW_HDMI_FC_AVICONF3 0x1017 | |||||
#define DW_HDMI_FC_GCP 0x1018 | |||||
#define DW_HDMI_FC_AVICONF0 0x1019 | |||||
#define DW_HDMI_FC_AVICONF1 0x101A | |||||
#define DW_HDMI_FC_AVICONF2 0x101B | |||||
#define DW_HDMI_FC_AVIDVID 0x101C | |||||
#define DW_HDMI_FC_AVIDETB0 0x101D | |||||
#define DW_HDMI_FC_AVIDETB1 0x101E | |||||
#define DW_HDMI_FC_AVISBB0 0x101F | |||||
#define DW_HDMI_FC_AVISBB1 0x1020 | |||||
#define DW_HDMI_FC_AVIELB0 0x1021 | |||||
#define DW_HDMI_FC_AVIELB1 0x1022 | |||||
#define DW_HDMI_FC_AVISRB0 0x1023 | |||||
#define DW_HDMI_FC_AVISRB1 0x1024 | |||||
#define DW_HDMI_FC_AUDICONF0 0x1025 | |||||
#define DW_HDMI_FC_AUDICONF1 0x1026 | |||||
#define DW_HDMI_FC_AUDICONF2 0x1027 | |||||
#define DW_HDMI_FC_AUDICONF3 0x1028 | |||||
#define DW_HDMI_FC_VSDIEEEID0 0x1029 | |||||
#define DW_HDMI_FC_VSDSIZE 0x102A | |||||
/* Main Controller */ | |||||
#define DW_HDMI_MC_CLKDIS 0x4001 | |||||
#define DW_HDMI_MC_CLKDIS_PIXELCLK (1 << 0) | |||||
#define DW_HDMI_MC_CLKDIS_TMDSCLK (1 << 1) | |||||
#define DW_HDMI_MC_CLKDIS_PREPCLK (1 << 2) | |||||
#define DW_HDMI_MC_CLKDIS_AUDCLK (1 << 3) | |||||
#define DW_HDMI_MC_CLKDIS_CSCCLK (1 << 4) | |||||
#define DW_HDMI_MC_CLKDIS_CECCLK (1 << 5) | |||||
#define DW_HDMI_MC_CLKDIS_HDCPCLK (1 << 6) | |||||
#define DW_HDMI_MC_SWRSTZREQ 0x4002 | |||||
#define DW_HDMI_MC_FLOWCTRL 0x4004 | |||||
#define DW_HDMI_MC_PHYRSTZ 0x4005 | |||||
#define DW_HDMI_MC_LOCKONCLOCK 0x4006 | |||||
#define DW_HDMI_MC_HEACPHY_RST 0x4007 | |||||
/* PHY I2CM */ | |||||
#define DW_HDMI_PHY_I2CM_INT_ADDR 0x3027 | |||||
#define DW_HDMI_PHY_I2CM_CTLINT_ADDR 0x3028 | |||||
/* I2CM */ | |||||
#define DW_HDMI_I2CM_SLAVE 0x7E00 | |||||
#define DW_HDMI_I2CM_ADDRESS 0x7E01 | |||||
#define DW_HDMI_I2CM_DATAO 0x7E02 | |||||
#define DW_HDMI_I2CM_DATAI 0x7E03 | |||||
#define DW_HDMI_I2CM_OP 0x7E04 | |||||
#define DW_HDMI_I2CM_OP_RD (1 << 0) | |||||
#define DW_HDMI_I2CM_OP_RDEXT (1 << 1) | |||||
#define DW_HDMI_I2CM_OP_WR (1 << 4) | |||||
#define DW_HDMI_I2CM_INT 0x7E05 | |||||
#define DW_HDMI_I2CM_INT_DONE_STATUS (1 << 0) | |||||
#define DW_HDMI_I2CM_INT_DONE_INT (1 << 1) | |||||
#define DW_HDMI_I2CM_INT_DONE_MASK (1 << 2) | |||||
#define DW_HDMI_I2CM_INT_DONE_POL (1 << 3) | |||||
#define DW_HDMI_I2CM_CLINT 0x7E06 | |||||
#define DW_HDMI_I2CM_CLINT_ARB_STATUS (1 << 0) | |||||
#define DW_HDMI_I2CM_CLINT_ARB_INT (1 << 1) | |||||
#define DW_HDMI_I2CM_CLINT_ARB_MASK (1 << 2) | |||||
#define DW_HDMI_I2CM_CLINT_ARB_POL (1 << 3) | |||||
#define DW_HDMI_I2CM_CLINT_NACK_STATUS (1 << 4) | |||||
#define DW_HDMI_I2CM_CLINT_NACK_INT (1 << 5) | |||||
#define DW_HDMI_I2CM_CLINT_NACK_MASK (1 << 6) | |||||
#define DW_HDMI_I2CM_CLINT_NACK_POL (1 << 7) | |||||
#define DW_HDMI_I2CM_DIV 0x7E07 | |||||
#define DW_HDMI_I2CM_DIV_FAST_MODE (1 << 3) | |||||
#define DW_HDMI_I2CM_SEGADDR 0x7E08 | |||||
#define DW_HDMI_I2CM_SOFTRSTZ 0x7E09 | |||||
#define DW_HDMI_I2CM_SOFTRSTZ_RST (1 << 0) | |||||
#define DW_HDMI_I2CM_SEGPTR 0x7E0A | |||||
#endif /* _DW_HDMI_H_ */ |