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head/sys/amd64/amd64/pmap.c

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Show First 20 Lines • Show All 6,125 Lines • ▼ Show 20 Lines if ((origpte & PG_MANAGED) != 0) {
/* /*
* The pmap lock is sufficient to synchronize with * The pmap lock is sufficient to synchronize with
* concurrent calls to pmap_page_test_mappings() and * concurrent calls to pmap_page_test_mappings() and
* pmap_ts_referenced(). * pmap_ts_referenced().
*/ */
if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
vm_page_dirty(om); vm_page_dirty(om);
if ((origpte & PG_A) != 0) if ((origpte & PG_A) != 0) {
pmap_invalidate_page(pmap, va);
vm_page_aflag_set(om, PGA_REFERENCED); vm_page_aflag_set(om, PGA_REFERENCED);
}
CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa); CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
pv = pmap_pvh_remove(&om->md, pmap, va); pv = pmap_pvh_remove(&om->md, pmap, va);
KASSERT(pv != NULL, KASSERT(pv != NULL,
("pmap_enter: no PV entry for %#lx", va)); ("pmap_enter: no PV entry for %#lx", va));
if ((newpte & PG_MANAGED) == 0) if ((newpte & PG_MANAGED) == 0)
free_pv_entry(pmap, pv); free_pv_entry(pmap, pv);
if ((om->a.flags & PGA_WRITEABLE) != 0 && if ((om->a.flags & PGA_WRITEABLE) != 0 &&
TAILQ_EMPTY(&om->md.pv_list) && TAILQ_EMPTY(&om->md.pv_list) &&
((om->flags & PG_FICTITIOUS) != 0 || ((om->flags & PG_FICTITIOUS) != 0 ||
TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list))) TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
vm_page_aflag_clear(om, PGA_WRITEABLE); vm_page_aflag_clear(om, PGA_WRITEABLE);
} } else {
if ((origpte & PG_A) != 0) /*
* Since this mapping is unmanaged, assume that PG_A
* is set.
*/
pmap_invalidate_page(pmap, va); pmap_invalidate_page(pmap, va);
}
origpte = 0; origpte = 0;
} else { } else {
/* /*
* Increment the counters. * Increment the counters.
*/ */
if ((newpte & PG_W) != 0) if ((newpte & PG_W) != 0)
pmap->pm_stats.wired_count++; pmap->pm_stats.wired_count++;
pmap_resident_count_inc(pmap, 1); pmap_resident_count_inc(pmap, 1);
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