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sys/arm64/arm64/locore.S
| Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines | _start: | ||||
| * x27 = TTBR0 table | * x27 = TTBR0 table | ||||
| * x26 = Kernel L1 table | * x26 = Kernel L1 table | ||||
| * x24 = TTBR1 table | * x24 = TTBR1 table | ||||
| */ | */ | ||||
| /* Enable the mmu */ | /* Enable the mmu */ | ||||
| bl start_mmu | bl start_mmu | ||||
| /* Load the new ttbr0 pagetable */ | |||||
| adr x27, pagetable_l0_ttbr0 | |||||
| /* Jump to the virtual address space */ | /* Jump to the virtual address space */ | ||||
| ldr x15, .Lvirtdone | ldr x15, .Lvirtdone | ||||
| br x15 | br x15 | ||||
| virtdone: | virtdone: | ||||
| /* Set up the stack */ | /* Set up the stack */ | ||||
| adr x25, initstack_end | adr x25, initstack_end | ||||
| mov sp, x25 | mov sp, x25 | ||||
| Show All 21 Lines | 1: | ||||
| neg x29, x29 | neg x29, x29 | ||||
| str x1, [x0] /* modulep */ | str x1, [x0] /* modulep */ | ||||
| str x26, [x0, 8] /* kern_l1pt */ | str x26, [x0, 8] /* kern_l1pt */ | ||||
| str x29, [x0, 16] /* kern_delta */ | str x29, [x0, 16] /* kern_delta */ | ||||
| adr x25, initstack | adr x25, initstack | ||||
| str x25, [x0, 24] /* kern_stack */ | str x25, [x0, 24] /* kern_stack */ | ||||
| str x24, [x0, 32] /* kern_l0pt */ | str x24, [x0, 32] /* kern_l0pt */ | ||||
| str x27, [x0, 40] /* kern_ttbr0 */ | |||||
| /* trace back starts here */ | /* trace back starts here */ | ||||
| mov fp, #0 | mov fp, #0 | ||||
| /* Branch to C code */ | /* Branch to C code */ | ||||
| bl initarm | bl initarm | ||||
| bl mi_startup | bl mi_startup | ||||
| /* We should not get here */ | /* We should not get here */ | ||||
| Show All 22 Lines | ENTRY(mpentry) | ||||
| bl drop_to_el1 | bl drop_to_el1 | ||||
| /* Set the context id */ | /* Set the context id */ | ||||
| msr contextidr_el1, xzr | msr contextidr_el1, xzr | ||||
| /* Load the kernel page table */ | /* Load the kernel page table */ | ||||
| adr x24, pagetable_l0_ttbr1 | adr x24, pagetable_l0_ttbr1 | ||||
| /* Load the identity page table */ | /* Load the identity page table */ | ||||
| adr x27, pagetable_l0_ttbr0 | adr x27, pagetable_l0_ttbr0_boostrap | ||||
| /* Enable the mmu */ | /* Enable the mmu */ | ||||
| bl start_mmu | bl start_mmu | ||||
| /* Load the new ttbr0 pagetable */ | |||||
| adr x27, pagetable_l0_ttbr0 | |||||
| /* Jump to the virtual address space */ | /* Jump to the virtual address space */ | ||||
| ldr x15, =mp_virtdone | ldr x15, =mp_virtdone | ||||
| br x15 | br x15 | ||||
| mp_virtdone: | mp_virtdone: | ||||
| ldr x4, =secondary_stacks | ldr x4, =secondary_stacks | ||||
| mov x5, #(PAGE_SIZE * KSTACK_PAGES) | mov x5, #(PAGE_SIZE * KSTACK_PAGES) | ||||
| mul x5, x0, x5 | mul x5, x0, x5 | ||||
| add sp, x4, x5 | add sp, x4, x5 | ||||
| /* Load the kernel ttbr0 pagetable */ | |||||
| msr ttbr0_el1, x27 | |||||
| isb | |||||
| /* Invalidate the TLB */ | |||||
| tlbi vmalle1 | |||||
| dsb sy | |||||
| isb | |||||
| b init_secondary | b init_secondary | ||||
| END(mpentry) | END(mpentry) | ||||
| #endif | #endif | ||||
| /* | /* | ||||
| * If we are started in EL2, configure the required hypervisor | * If we are started in EL2, configure the required hypervisor | ||||
| * registers and drop to EL1. | * registers and drop to EL1. | ||||
| */ | */ | ||||
| ▲ Show 20 Lines • Show All 391 Lines • ▼ Show 20 Lines | start_mmu: | ||||
| msr ttbr0_el1, x27 | msr ttbr0_el1, x27 | ||||
| msr ttbr1_el1, x24 | msr ttbr1_el1, x24 | ||||
| isb | isb | ||||
| /* Clear the Monitor Debug System control register */ | /* Clear the Monitor Debug System control register */ | ||||
| msr mdscr_el1, xzr | msr mdscr_el1, xzr | ||||
| /* Invalidate the TLB */ | /* Invalidate the TLB */ | ||||
| tlbi vmalle1is | tlbi vmalle1is | ||||
alc: Should we have a dsb instruction here to ensure that the invalidation has completed before… | |||||
| ldr x2, mair | ldr x2, mair | ||||
| msr mair_el1, x2 | msr mair_el1, x2 | ||||
| /* | /* | ||||
| * Setup TCR according to the PARange and ASIDBits fields | * Setup TCR according to the PARange and ASIDBits fields | ||||
| * from ID_AA64MMFR0_EL1. More precisely, set TCR_EL1.AS | * from ID_AA64MMFR0_EL1. More precisely, set TCR_EL1.AS | ||||
| * to 1 only if the ASIDBits field equals 0b0010. | * to 1 only if the ASIDBits field equals 0b0010. | ||||
| Show All 40 Lines | sctlr_clear: | ||||
| .globl abort | .globl abort | ||||
| abort: | abort: | ||||
| b abort | b abort | ||||
| //.section .init_pagetable | //.section .init_pagetable | ||||
| .align 12 /* 4KiB aligned */ | .align 12 /* 4KiB aligned */ | ||||
| /* | /* | ||||
| * 3 initial tables (in the following order): | * 6 initial tables (in the following order): | ||||
| * L2 for kernel (High addresses) | * L2 for kernel (High addresses) | ||||
| * L1 for kernel | * L1 for kernel | ||||
| * L1 for user (Low addresses) | * L0 for kernel | ||||
| * L1 bootstrap for user (Low addresses) | |||||
| * L0 bootstrap for user | |||||
| * L0 for user | |||||
| */ | */ | ||||
| pagetable: | pagetable: | ||||
| .space PAGE_SIZE | .space PAGE_SIZE | ||||
| pagetable_l1_ttbr1: | pagetable_l1_ttbr1: | ||||
| .space PAGE_SIZE | .space PAGE_SIZE | ||||
| pagetable_l0_ttbr1: | pagetable_l0_ttbr1: | ||||
| .space PAGE_SIZE | .space PAGE_SIZE | ||||
| pagetable_l1_ttbr0: | pagetable_l1_ttbr0_bootstrap: | ||||
| .space PAGE_SIZE | |||||
| pagetable_l0_ttbr0_boostrap: | |||||
| .space PAGE_SIZE | .space PAGE_SIZE | ||||
| pagetable_l0_ttbr0: | pagetable_l0_ttbr0: | ||||
| .space PAGE_SIZE | .space PAGE_SIZE | ||||
| .globl pagetable_dmap | .globl pagetable_dmap | ||||
| pagetable_dmap: | pagetable_dmap: | ||||
| .space PAGE_SIZE * DMAP_TABLES | .space PAGE_SIZE * DMAP_TABLES | ||||
| pagetable_end: | pagetable_end: | ||||
| ▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines | |||||
Should we have a dsb instruction here to ensure that the invalidation has completed before setting the SCTLR register below?