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sys/dev/e1000/e1000_defines.h
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#define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */ | #define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */ | ||||
#define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */ | #define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */ | ||||
#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ | #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ | ||||
#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ | #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ | ||||
#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ | #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ | ||||
#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ | #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ | ||||
#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ | #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ | ||||
#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ | #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ | ||||
#define E1000_RCTL_RDMTS_HEX 0x00010000 | |||||
#define E1000_RCTL_RDMTS1_HEX E1000_RCTL_RDMTS_HEX | |||||
#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ | #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ | ||||
#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ | #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ | ||||
#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ | #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ | ||||
/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ | /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ | ||||
#define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ | #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ | ||||
#define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ | #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ | ||||
#define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ | #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ | ||||
#define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ | #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ | ||||
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#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ | #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ | ||||
#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ | #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ | ||||
#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ | #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ | ||||
#define E1000_ICR_FER 0x00400000 /* Fatal Error */ | #define E1000_ICR_FER 0x00400000 /* Fatal Error */ | ||||
#define E1000_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/ | #define E1000_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/ | ||||
#define E1000_ICR_MDDET 0x10000000 /* Malicious Driver Detect */ | #define E1000_ICR_MDDET 0x10000000 /* Malicious Driver Detect */ | ||||
#define E1000_ITR_MASK 0x000FFFFF /* ITR value bitfield */ | |||||
#define E1000_ITR_MULT 256 /* ITR mulitplier in nsec */ | |||||
/* PBA ECC Register */ | /* PBA ECC Register */ | ||||
#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ | #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ | ||||
#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ | #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ | ||||
#define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ | #define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ | ||||
#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ | #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ | ||||
#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ | #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ | ||||
/* Extended Interrupt Cause Read */ | /* Extended Interrupt Cause Read */ | ||||
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#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ | #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ | ||||
#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ | #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ | ||||
#define E1000_RXCW_C 0x20000000 /* Receive config */ | #define E1000_RXCW_C 0x20000000 /* Receive config */ | ||||
#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ | #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ | ||||
#define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ | #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ | ||||
#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ | #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ | ||||
/* HH Time Sync */ | |||||
#define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */ | |||||
#define E1000_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000 /* sync err */ | |||||
#define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */ | |||||
#define E1000_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */ | |||||
#define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ | #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ | ||||
#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ | #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ | ||||
#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 | #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 | ||||
#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 | #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 | ||||
#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 | #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 | ||||
#define E1000_TSYNCRXCTL_TYPE_ALL 0x08 | #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 | ||||
#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A | #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A | ||||
#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ | #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ | ||||
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#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ | #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ | ||||
#define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */ | #define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */ | ||||
#define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */ | #define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */ | ||||
#define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */ | #define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */ | ||||
#define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */ | #define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */ | ||||
/* NVM Addressing bits based on type 0=small, 1=large */ | /* NVM Addressing bits based on type 0=small, 1=large */ | ||||
#define E1000_EECD_ADDR_BITS 0x00000400 | #define E1000_EECD_ADDR_BITS 0x00000400 | ||||
#define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ | #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ | ||||
#ifndef E1000_NVM_GRANT_ATTEMPTS | |||||
#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ | #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ | ||||
#endif | |||||
#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ | #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ | ||||
#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ | #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ | ||||
#define E1000_EECD_SIZE_EX_SHIFT 11 | #define E1000_EECD_SIZE_EX_SHIFT 11 | ||||
#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ | #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ | ||||
#define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ | #define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ | ||||
#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ | #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ | ||||
#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) | #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) | ||||
#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ | #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ | ||||
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#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ | #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ | ||||
#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ | #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ | ||||
#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ | #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ | ||||
#define E1000_FLASH_UPDATES 2000 | #define E1000_FLASH_UPDATES 2000 | ||||
/* NVM Word Offsets */ | /* NVM Word Offsets */ | ||||
#define NVM_COMPAT 0x0003 | #define NVM_COMPAT 0x0003 | ||||
#define NVM_ID_LED_SETTINGS 0x0004 | #define NVM_ID_LED_SETTINGS 0x0004 | ||||
#define NVM_VERSION 0x0005 | |||||
#define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ | #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ | ||||
#define NVM_PHY_CLASS_WORD 0x0007 | #define NVM_PHY_CLASS_WORD 0x0007 | ||||
#define E1000_I210_NVM_FW_MODULE_PTR 0x0010 | #define E1000_I210_NVM_FW_MODULE_PTR 0x0010 | ||||
#define E1000_I350_NVM_FW_MODULE_PTR 0x0051 | #define E1000_I350_NVM_FW_MODULE_PTR 0x0051 | ||||
#define NVM_FUTURE_INIT_WORD1 0x0019 | #define NVM_FUTURE_INIT_WORD1 0x0019 | ||||
#define NVM_ETRACK_WORD 0x0042 | |||||
#define NVM_ETRACK_HIWORD 0x0043 | |||||
#define NVM_COMB_VER_OFF 0x0083 | |||||
#define NVM_COMB_VER_PTR 0x003d | |||||
/* NVM version defines */ | |||||
#define NVM_MAJOR_MASK 0xF000 | |||||
#define NVM_MINOR_MASK 0x0FF0 | |||||
#define NVM_IMAGE_ID_MASK 0x000F | |||||
#define NVM_COMB_VER_MASK 0x00FF | |||||
#define NVM_MAJOR_SHIFT 12 | |||||
#define NVM_MINOR_SHIFT 4 | |||||
#define NVM_COMB_VER_SHFT 8 | |||||
#define NVM_VER_INVALID 0xFFFF | |||||
#define NVM_ETRACK_SHIFT 16 | |||||
#define NVM_ETRACK_VALID 0x8000 | |||||
#define NVM_NEW_DEC_MASK 0x0F00 | |||||
#define NVM_HEX_CONV 16 | |||||
#define NVM_HEX_TENS 10 | |||||
/* FW version defines */ | |||||
/* Offset of "Loader patch ptr" in Firmware Header */ | |||||
#define E1000_I350_NVM_FW_LOADER_PATCH_PTR_OFFSET 0x01 | |||||
/* Patch generation hour & minutes */ | |||||
#define E1000_I350_NVM_FW_VER_WORD1_OFFSET 0x04 | |||||
/* Patch generation month & day */ | |||||
#define E1000_I350_NVM_FW_VER_WORD2_OFFSET 0x05 | |||||
/* Patch generation year */ | |||||
#define E1000_I350_NVM_FW_VER_WORD3_OFFSET 0x06 | |||||
/* Patch major & minor numbers */ | |||||
#define E1000_I350_NVM_FW_VER_WORD4_OFFSET 0x07 | |||||
#define NVM_MAC_ADDR 0x0000 | #define NVM_MAC_ADDR 0x0000 | ||||
#define NVM_SUB_DEV_ID 0x000B | #define NVM_SUB_DEV_ID 0x000B | ||||
#define NVM_SUB_VEN_ID 0x000C | #define NVM_SUB_VEN_ID 0x000C | ||||
#define NVM_DEV_ID 0x000D | #define NVM_DEV_ID 0x000D | ||||
#define NVM_VEN_ID 0x000E | #define NVM_VEN_ID 0x000E | ||||
#define NVM_INIT_CTRL_2 0x000F | #define NVM_INIT_CTRL_2 0x000F | ||||
#define NVM_INIT_CTRL_4 0x0013 | #define NVM_INIT_CTRL_4 0x0013 | ||||
#define NVM_LED_1_CFG 0x001C | #define NVM_LED_1_CFG 0x001C | ||||
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#define E1000_PCIEMISC_LX_DECISION 0x00000080 | #define E1000_PCIEMISC_LX_DECISION 0x00000080 | ||||
#define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */ | #define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */ | ||||
#define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */ | #define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */ | ||||
#define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */ | #define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */ | ||||
#define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ | #define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ | ||||
#define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ | #define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ | ||||
#define E1000_DOBFFCTL_OBFFTHR_MASK 0x000000FF /* OBFF threshold */ | |||||
#define E1000_DOBFFCTL_EXIT_ACT_MASK 0x01000000 /* Exit active CB */ | |||||
/* Proxy Filter Control */ | /* Proxy Filter Control */ | ||||
#define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */ | #define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */ | ||||
#define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */ | #define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */ | ||||
#define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */ | #define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */ | ||||
#define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */ | #define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */ | ||||
#define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */ | #define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */ | ||||
#define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */ | #define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */ | ||||
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