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ioat.h
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*/ | */ | ||||
#define DMA_NO_WAIT 0x2 | #define DMA_NO_WAIT 0x2 | ||||
/* | /* | ||||
* Disallow prefetching the source of the following operation. Ordinarily, DMA | * Disallow prefetching the source of the following operation. Ordinarily, DMA | ||||
* operations can be pipelined on some hardware. E.g., operation 2's source | * operations can be pipelined on some hardware. E.g., operation 2's source | ||||
* may be prefetched before operation 1 completes. | * may be prefetched before operation 1 completes. | ||||
*/ | */ | ||||
#define DMA_FENCE 0x4 | #define DMA_FENCE 0x4 | ||||
#define _DMA_GENERIC_FLAGS (DMA_INT_EN | DMA_NO_WAIT | DMA_FENCE) | |||||
/* | /* | ||||
* Emit a CRC32C as the result of a ioat_copy_crc() or ioat_crc(). | * Emit a CRC32C as the result of a ioat_copy_crc() or ioat_crc(). | ||||
*/ | */ | ||||
#define DMA_CRC_STORE 0x8 | #define DMA_CRC_STORE 0x8 | ||||
/* | /* | ||||
* Compare the CRC32C of a ioat_copy_crc() or ioat_crc() against an expeceted | * Compare the CRC32C of a ioat_copy_crc() or ioat_crc() against an expeceted | ||||
* value. It is invalid to specify both TEST and STORE. | * value. It is invalid to specify both TEST and STORE. | ||||
*/ | */ | ||||
#define DMA_CRC_TEST 0x10 | #define DMA_CRC_TEST 0x10 | ||||
#define _DMA_CRC_TESTSTORE (DMA_CRC_STORE | DMA_CRC_TEST) | #define _DMA_CRC_TESTSTORE (DMA_CRC_STORE | DMA_CRC_TEST) | ||||
/* | /* | ||||
* Use an inline comparison CRC32C or emit an inline CRC32C result. Invalid | * Use an inline comparison CRC32C or emit an inline CRC32C result. Invalid | ||||
* without one of STORE or TEST. | * without one of STORE or TEST. | ||||
*/ | */ | ||||
#define DMA_CRC_INLINE 0x20 | #define DMA_CRC_INLINE 0x20 | ||||
#define _DMA_CRC_FLAGS (DMA_CRC_STORE | DMA_CRC_TEST | DMA_CRC_INLINE) | |||||
/* | /* | ||||
* src, dst and/or crc address arguments are already loaded into bus_dma(9) | |||||
* map, parented by tag returned by ioat_get_dma_tag() for the device. | |||||
*/ | |||||
#define DMA_SRC_LOADED 0x100 | |||||
#define DMA_DST_LOADED 0x200 | |||||
#define DMA_CRC_LOADED 0x400 | |||||
#define _DMA_GENERIC_FLAGS (DMA_INT_EN | DMA_NO_WAIT | DMA_FENCE | \ | |||||
DMA_SRC_LOADED | DMA_DST_LOADED) | |||||
#define _DMA_CRC_FLAGS (DMA_CRC_STORE | DMA_CRC_TEST | DMA_CRC_INLINE | \ | |||||
DMA_CRC_LOADED) | |||||
/* | |||||
* Hardware revision number. Different hardware revisions support different | * Hardware revision number. Different hardware revisions support different | ||||
* features. For example, 3.2 cannot read from MMIO space, while 3.3 can. | * features. For example, 3.2 cannot read from MMIO space, while 3.3 can. | ||||
*/ | */ | ||||
#define IOAT_VER_3_0 0x30 | #define IOAT_VER_3_0 0x30 | ||||
#define IOAT_VER_3_2 0x32 | #define IOAT_VER_3_2 0x32 | ||||
#define IOAT_VER_3_3 0x33 | #define IOAT_VER_3_3 0x33 | ||||
/* | /* | ||||
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines | |||||
/* Release the DMA channel */ | /* Release the DMA channel */ | ||||
void ioat_put_dmaengine(bus_dmaengine_t dmaengine); | void ioat_put_dmaengine(bus_dmaengine_t dmaengine); | ||||
/* Check the DMA engine's HW version */ | /* Check the DMA engine's HW version */ | ||||
int ioat_get_hwversion(bus_dmaengine_t dmaengine); | int ioat_get_hwversion(bus_dmaengine_t dmaengine); | ||||
size_t ioat_get_max_io_size(bus_dmaengine_t dmaengine); | size_t ioat_get_max_io_size(bus_dmaengine_t dmaengine); | ||||
uint32_t ioat_get_capabilities(bus_dmaengine_t dmaengine); | uint32_t ioat_get_capabilities(bus_dmaengine_t dmaengine); | ||||
bus_dma_tag_t ioat_get_dma_tag(bus_dmaengine_t dmaengine); | |||||
int ioat_get_domain(bus_dmaengine_t dmaengine, int *domain); | |||||
/* | /* | ||||
* Set interrupt coalescing on a DMA channel. | * Set interrupt coalescing on a DMA channel. | ||||
* | * | ||||
* The argument is in microseconds. A zero value disables coalescing. Any | * The argument is in microseconds. A zero value disables coalescing. Any | ||||
* other value delays interrupt generation for N microseconds to provide | * other value delays interrupt generation for N microseconds to provide | ||||
* opportunity to coalesce multiple operations into a single interrupt. | * opportunity to coalesce multiple operations into a single interrupt. | ||||
* | * | ||||
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