Differential D22241 Diff 63957 sys/arm64/arm64/locore.S

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sys/arm64/arm64/locore.S

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#include "assym.inc"		#include "assym.inc"
#include "opt_kstack_pages.h"		#include "opt_kstack_pages.h"
#include <sys/syscall.h>		#include <sys/syscall.h>
#include <machine/asm.h>		#include <machine/asm.h>
#include <machine/armreg.h>		#include <machine/armreg.h>
#include <machine/hypervisor.h>		#include <machine/hypervisor.h>
#include <machine/param.h>		#include <machine/param.h>
#include <machine/pte.h>		#include <machine/pte.h>
		#include <machine/vm.h>
#include <machine/vmparam.h>		#include <machine/vmparam.h>

#define VIRT_BITS 48		#define VIRT_BITS 48
#define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)		#define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)

.globl kernbase		.globl kernbase
.set kernbase, KERNBASE		.set kernbase, KERNBASE

#define DEVICE_MEM 0
#define NORMAL_UNCACHED 1
#define NORMAL_MEM 2

/*		/*
* We assume:		* We assume:
* MMU on with an identity map, or off		* MMU on with an identity map, or off
* D-Cache: off		* D-Cache: off
* I-Cache: on or off		* I-Cache: on or off
* We are loaded at a 2MiB aligned address		* We are loaded at a 2MiB aligned address
*/		*/

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/* Add two 2MiB pages for the module data and round up */		/* Add two 2MiB pages for the module data and round up */
ldr x7, =(3 * L2_SIZE - 1)		ldr x7, =(3 * L2_SIZE - 1)
add x8, x8, x7		add x8, x8, x7
/* Get the number of l2 pages to allocate, rounded down */		/* Get the number of l2 pages to allocate, rounded down */
lsr x10, x8, #(L2_SHIFT)		lsr x10, x8, #(L2_SHIFT)

/* Create the kernel space L2 table */		/* Create the kernel space L2 table */
mov x6, x26		mov x6, x26
mov x7, #NORMAL_MEM		mov x7, #VM_MEMATTR_WRITE_BACK
mov x8, #(KERNBASE & L2_BLOCK_MASK)		mov x8, #(KERNBASE & L2_BLOCK_MASK)
mov x9, x28		mov x9, x28
bl build_l2_block_pagetable		bl build_l2_block_pagetable

/* Move to the l1 table */		/* Move to the l1 table */
add x26, x26, #PAGE_SIZE		add x26, x26, #PAGE_SIZE

/* Link the l1 -> l2 table */		/* Link the l1 -> l2 table */
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* Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_nG.		* Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_nG.
* They are only needed early on, so the VA = PA map is uncached.		* They are only needed early on, so the VA = PA map is uncached.
*/		*/
add x27, x24, #PAGE_SIZE		add x27, x24, #PAGE_SIZE

mov x6, x27 /* The initial page table */		mov x6, x27 /* The initial page table */
#if defined(SOCDEV_PA) && defined(SOCDEV_VA)		#if defined(SOCDEV_PA) && defined(SOCDEV_VA)
/* Create a table for the UART */		/* Create a table for the UART */
mov x7, #(ATTR_nG \| ATTR_IDX(DEVICE_MEM))		mov x7, #(ATTR_nG \| ATTR_IDX(VM_MEMATTR_DEVICE))
mov x8, #(SOCDEV_VA) /* VA start */		mov x8, #(SOCDEV_VA) /* VA start */
mov x9, #(SOCDEV_PA) /* PA start */		mov x9, #(SOCDEV_PA) /* PA start */
mov x10, #1		mov x10, #1
bl build_l1_block_pagetable		bl build_l1_block_pagetable
#endif		#endif

/* Create the VA = PA map */		/*
mov x7, #(ATTR_nG \| ATTR_IDX(NORMAL_UNCACHED))		* Create the VA = PA map
		*/
		mov x9, #(ATTR_nG \| ATTR_IDX(M_MEMATTR_UNCACHEABLE))
mov x9, x27		mov x9, x27
mov x8, x9 /* VA start (== PA start) */		mov x8, x9 /* VA start (== PA start) */
mov x10, #1		mov x10, #1
bl build_l1_block_pagetable		bl build_l1_block_pagetable

/* Move to the l0 table */		/* Move to the l0 table */
add x27, x27, #PAGE_SIZE		add x27, x27, #PAGE_SIZE

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orr x1, x1, x2 /* Set the required bits */		orr x1, x1, x2 /* Set the required bits */
msr sctlr_el1, x1		msr sctlr_el1, x1
isb		isb

ret		ret

.align 3		.align 3
mair:		mair:
.quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, 0) \| \		.quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE) \| \
MAIR_ATTR(MAIR_NORMAL_NC, 1) \| \		MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) \| \
MAIR_ATTR(MAIR_NORMAL_WB, 2) \| \		MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) \| \
MAIR_ATTR(MAIR_NORMAL_WT, 3)		MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH)
tcr:		tcr:
.quad (TCR_TxSZ(64 - VIRT_BITS) \| TCR_TG1_4K \| \		.quad (TCR_TxSZ(64 - VIRT_BITS) \| TCR_TG1_4K \| \
TCR_CACHE_ATTRS \| TCR_SMP_ATTRS)		TCR_CACHE_ATTRS \| TCR_SMP_ATTRS)
sctlr_set:		sctlr_set:
/* Bits to set */		/* Bits to set */
.quad (SCTLR_LSMAOE \| SCTLR_nTLSMD \| SCTLR_UCI \| SCTLR_SPAN \| \		.quad (SCTLR_LSMAOE \| SCTLR_nTLSMD \| SCTLR_UCI \| SCTLR_SPAN \| \
SCTLR_nTWE \| SCTLR_nTWI \| SCTLR_UCT \| SCTLR_DZE \| \		SCTLR_nTWE \| SCTLR_nTWI \| SCTLR_UCT \| SCTLR_DZE \| \
SCTLR_I \| SCTLR_SED \| SCTLR_SA0 \| SCTLR_SA \| SCTLR_C \| \		SCTLR_I \| SCTLR_SED \| SCTLR_SA0 \| SCTLR_SA \| SCTLR_C \| \
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