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sys/dev/ioat/ioat_hw.h
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/*- | |||||
* Copyright (C) 2012 Intel Corporation | |||||
* All rights reserved. | |||||
* | |||||
* Redistribution and use in source and binary forms, with or without | |||||
* modification, are permitted provided that the following conditions | |||||
* are met: | |||||
* 1. Redistributions of source code must retain the above copyright | |||||
* notice, this list of conditions and the following disclaimer. | |||||
* 2. Redistributions in binary form must reproduce the above copyright | |||||
* notice, this list of conditions and the following disclaimer in the | |||||
* documentation and/or other materials provided with the distribution. | |||||
* | |||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND | |||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE | |||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |||||
* SUCH DAMAGE. | |||||
*/ | |||||
#ifndef __IOAT_HW_H__ | |||||
#define __IOAT_HW_H__ | |||||
#define IOAT_MAX_CHANNELS 32 | |||||
#define IOAT_CHANCNT_OFFSET 0x00 | |||||
#define IOAT_XFERCAP_OFFSET 0x01 | |||||
#define IOAT_GENCTRL_OFFSET 0x02 | |||||
#define IOAT_INTRCTRL_OFFSET 0x03 | |||||
#define IOAT_INTRCTRL_MASTER_INT_EN 0x01 | |||||
#define IOAT_ATTNSTATUS_OFFSET 0x04 | |||||
#define IOAT_CBVER_OFFSET 0x08 | |||||
#define IOAT_VER_3_0 0x30 | |||||
#define IOAT_VER_3_3 0x33 | |||||
#define IOAT_INTRDELAY_OFFSET 0x0C | |||||
#define IOAT_CS_STATUS_OFFSET 0x0E | |||||
#define IOAT_DMACAPABILITY_OFFSET 0x10 | |||||
/* DMA Channel Registers */ | |||||
#define IOAT_CHANCTRL_OFFSET 0x80 | |||||
#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000 | |||||
#define IOAT_CHANCTRL_COMPL_DCA_EN 0x0200 | |||||
#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 | |||||
#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 | |||||
#define IOAT_CHANCTRL_ERR_INT_EN 0x0010 | |||||
#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 | |||||
#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 | |||||
#define IOAT_CHANCTRL_INT_REARM 0x0001 | |||||
#define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\ | |||||
IOAT_CHANCTRL_ANY_ERR_ABORT_EN) | |||||
#define IOAT_CHANCMD_OFFSET 0x84 | |||||
#define IOAT_CHANCMD_RESET 0x20 | |||||
#define IOAT_CHANCMD_SUSPEND 0x04 | |||||
#define IOAT_DMACOUNT_OFFSET 0x86 | |||||
#define IOAT_CHANSTS_OFFSET_LOW 0x88 | |||||
#define IOAT_CHANSTS_OFFSET_HIGH 0x8C | |||||
#define IOAT_CHANSTS_OFFSET 0x88 | |||||
#define IOAT_CHANSTS_STATUS 0x7ULL | |||||
#define IOAT_CHANSTS_ACTIVE 0x0 | |||||
#define IOAT_CHANSTS_IDLE 0x1 | |||||
#define IOAT_CHANSTS_SUSPENDED 0x2 | |||||
#define IOAT_CHANSTS_HALTED 0x3 | |||||
#define IOAT_CHANSTS_UNAFFILIATED_ERROR 0x8ULL | |||||
#define IOAT_CHANSTS_SOFT_ERROR 0x10ULL | |||||
#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK (~0x3FULL) | |||||
#define IOAT_CHAINADDR_OFFSET_LOW 0x90 | |||||
#define IOAT_CHAINADDR_OFFSET_HIGH 0x94 | |||||
#define IOAT_CHANCMP_OFFSET_LOW 0x98 | |||||
#define IOAT_CHANCMP_OFFSET_HIGH 0x9C | |||||
#define IOAT_CHANERR_OFFSET 0xA8 | |||||
#define IOAT_CFG_CHANERR_INT_OFFSET 0x180 | |||||
#define IOAT_CFG_CHANERRMASK_INT_OFFSET 0x184 | |||||
#define IOAT_MIN_ORDER 4 | |||||
#define IOAT_MAX_ORDER 16 | |||||
#endif /* __IOAT_HW_H__ */ |