Differential D22016 Diff 63722 sys/dev/ichiic/ig4_reg.h

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sys/dev/ichiic/ig4_reg.h

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	#define IG4_REG_TX_ABRT_SOURCE 0x0080 /* RO Transmit Abort Source */			#define IG4_REG_TX_ABRT_SOURCE 0x0080 /* RO Transmit Abort Source */
	#define IG4_REG_SLV_DATA_NACK 0x0084 /* RW General Slave Data NACK */			#define IG4_REG_SLV_DATA_NACK 0x0084 /* RW General Slave Data NACK */
	#define IG4_REG_DMA_CTRL 0x0088 /* RW DMA Control */			#define IG4_REG_DMA_CTRL 0x0088 /* RW DMA Control */
	#define IG4_REG_DMA_TDLR 0x008C /* RW DMA Transmit Data Level */			#define IG4_REG_DMA_TDLR 0x008C /* RW DMA Transmit Data Level */
	#define IG4_REG_DMA_RDLR 0x0090 /* RW DMA Receive Data Level */			#define IG4_REG_DMA_RDLR 0x0090 /* RW DMA Receive Data Level */
	#define IG4_REG_SDA_SETUP 0x0094 /* RW SDA Setup */			#define IG4_REG_SDA_SETUP 0x0094 /* RW SDA Setup */
	#define IG4_REG_ACK_GENERAL_CALL 0x0098 /* RW I2C ACK General Call */			#define IG4_REG_ACK_GENERAL_CALL 0x0098 /* RW I2C ACK General Call */
	#define IG4_REG_ENABLE_STATUS 0x009C /* RO Enable Status */			#define IG4_REG_ENABLE_STATUS 0x009C /* RO Enable Status */
	/* Available at least on Atom SoCs and Haswell mobile. */			/* Available at least on Atom SoCs, Haswell mobile and some Skylakes. */
	#define IG4_REG_COMP_PARAM1 0x00F4 /* RO Component Parameter */			#define IG4_REG_COMP_PARAM1 0x00F4 /* RO Component Parameter */
	#define IG4_REG_COMP_VER 0x00F8 /* RO Component Version */			#define IG4_REG_COMP_VER 0x00F8 /* RO Component Version */
	/* Available at least on Atom SoCs */			/* Available at least on Atom SoCs */
	#define IG4_REG_COMP_TYPE 0x00FC /* RO Probe width/endian? (linux) */			#define IG4_REG_COMP_TYPE 0x00FC /* RO Probe width/endian? (linux) */
	/* Available on Skylake-U/Y and Kaby Lake-U/Y */			/* 0x200-0x2FF - Additional registers available on Skylake-U/Y and others */
	#define IG4_REG_RESETS_SKL 0x0204 /* RW Reset Register */			#define IG4_REG_RESETS_SKL 0x0204 /* RW Reset Register */
	#define IG4_REG_ACTIVE_LTR_VALUE 0x0210 /* RW Active LTR Value */			#define IG4_REG_ACTIVE_LTR_VALUE 0x0210 /* RW Active LTR Value */
	#define IG4_REG_IDLE_LTR_VALUE 0x0214 /* RW Idle LTR Value */			#define IG4_REG_IDLE_LTR_VALUE 0x0214 /* RW Idle LTR Value */
	#define IG4_REG_TX_ACK_COUNT 0x0218 /* RO TX ACK Count */			#define IG4_REG_TX_ACK_COUNT 0x0218 /* RO TX ACK Count */
	#define IG4_REG_RX_BYTE_COUNT 0x021C /* RO RX ACK Count */			#define IG4_REG_RX_BYTE_COUNT 0x021C /* RO RX ACK Count */
	#define IG4_REG_DEVIDLE_CTRL 0x024C /* RW Device Control */			#define IG4_REG_DEVIDLE_CTRL 0x024C /* RW Device Control */
	/* Available at least on Atom SoCs */			/* Available at least on Atom SoCs */
	#define IG4_REG_CLK_PARMS 0x0800 /* RW Clock Parameters */			#define IG4_REG_CLK_PARMS 0x0800 /* RW Clock Parameters */
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	* Performing a read operation with a 10-bit address			* Performing a read operation with a 10-bit address
	*			*
	* Attempting to perform the above operations will result in the			* Attempting to perform the above operations will result in the
	* TX_ABORT bit being set in RAW_INTR_STAT.			* TX_ABORT bit being set in RAW_INTR_STAT.
	*/			*/
	#define IG4_CTL_SLAVE_DISABLE 0x0040 /* snarfed from linux */			#define IG4_CTL_SLAVE_DISABLE 0x0040 /* snarfed from linux */
	#define IG4_CTL_RESTARTEN 0x0020 /* Allow Restart when master */			#define IG4_CTL_RESTARTEN 0x0020 /* Allow Restart when master */
	#define IG4_CTL_10BIT 0x0010 /* ctlr accepts 10-bit addresses */			#define IG4_CTL_10BIT 0x0010 /* ctlr accepts 10-bit addresses */
				#define IG4_CTL_SPEED_MASK 0x0006 /* speed at which the I2C operates */
				#define IG4_CTL_MASTER 0x0001 /* snarfed from linux */

				#define IG4_CTL_SPEED_HIGH 0x0006 /* snarfed from linux */
	#define IG4_CTL_SPEED_FAST 0x0004 /* snarfed from linux */			#define IG4_CTL_SPEED_FAST 0x0004 /* snarfed from linux */
	#define IG4_CTL_SPEED_STD 0x0002 /* snarfed from linux */			#define IG4_CTL_SPEED_STD 0x0002 /* snarfed from linux */
	#define IG4_CTL_MASTER 0x0001 /* snarfed from linux */

	/*			/*
	* TAR_ADD - Target Address Register 22.2.2			* TAR_ADD - Target Address Register 22.2.2
	* Default Value: 0x00000055F			* Default Value: 0x00000055F
	*			*
	* 10BIT - RW controller starts its transfers in 10-bit			* 10BIT - RW controller starts its transfers in 10-bit
	* address mode, else 7-bit.			* address mode, else 7-bit.
	*			*
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	#define IG4_INTR_ACTIVITY 0x0100			#define IG4_INTR_ACTIVITY 0x0100
	#define IG4_INTR_TX_ABRT 0x0040			#define IG4_INTR_TX_ABRT 0x0040
	#define IG4_INTR_TX_EMPTY 0x0010			#define IG4_INTR_TX_EMPTY 0x0010
	#define IG4_INTR_TX_OVER 0x0008			#define IG4_INTR_TX_OVER 0x0008
	#define IG4_INTR_RX_FULL 0x0004			#define IG4_INTR_RX_FULL 0x0004
	#define IG4_INTR_RX_OVER 0x0002			#define IG4_INTR_RX_OVER 0x0002
	#define IG4_INTR_RX_UNDER 0x0001			#define IG4_INTR_RX_UNDER 0x0001

				#define IG4_INTR_ERR_MASK (IG4_INTR_TX_ABRT \| IG4_INTR_TX_OVER \| \
				IG4_INTR_RX_OVER \| IG4_INTR_RX_UNDER)

	/*			/*
	* RX_TL - (RW) Receive FIFO Threshold Register 22.2.11			* RX_TL - (RW) Receive FIFO Threshold Register 22.2.11
	* TX_TL - (RW) Transmit FIFO Threshold Register 22.2.12			* TX_TL - (RW) Transmit FIFO Threshold Register 22.2.12
	*			*
	* Specify the receive and transmit FIFO threshold register. The			* Specify the receive and transmit FIFO threshold register. The
	* FIFOs have 16 elements. The valid range is 0-15. Setting a			* FIFOs have 16 elements. The valid range is 0-15. Setting a
	* value greater than 15 causes the actual value to be the maximum			* value greater than 15 causes the actual value to be the maximum
	* depth of the FIFO.			* depth of the FIFO.
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	* there is no further activity on the bus.			* there is no further activity on the bus.
	*/			*/
	#define IG4_CLR_BIT 0x0001 /* Reflects source */			#define IG4_CLR_BIT 0x0001 /* Reflects source */

	/*			/*
	* I2C_EN - (RW) I2C Enable Register 22.2.22			* I2C_EN - (RW) I2C Enable Register 22.2.22
	*			*
	* ABORT Software can abort an I2C transfer by setting this			* ABORT Software can abort an I2C transfer by setting this
	* bit. Hardware will clear the bit once the STOP has			* bit. In response, the controller issues the STOP
				* condition over the I2C bus, followed by TX FIFO flush.
				* Hardware will clear the bit once the STOP has
	* been detected. This bit can only be set while the			* been detected. This bit can only be set while the
	* I2C interface is enabled.			* I2C interface is enabled.
	*			*
	* I2C_ENABLE Enable the controller, else disable it.			* I2C_ENABLE Enable the controller, else disable it.
	* (Use I2C_ENABLE_STATUS to poll enable status			* (Use I2C_ENABLE_STATUS to poll enable status
	* & wait for changes)			* & wait for changes)
	*/			*/
	#define IG4_I2C_ABORT 0x0002			#define IG4_I2C_ABORT 0x0002
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	/*			/*
	* TXFLR - (RO) Transmit FIFO Level Register 22.2.24			* TXFLR - (RO) Transmit FIFO Level Register 22.2.24
	* RXFLR - (RO) Receive FIFO Level Register 22.2.25			* RXFLR - (RO) Receive FIFO Level Register 22.2.25
	*			*
	* Read the number of entries currently in the Transmit or Receive			* Read the number of entries currently in the Transmit or Receive
	* FIFOs. Note that for some reason the mask is 9 bits instead of			* FIFOs. Note that for some reason the mask is 9 bits instead of
	* the 8 bits the fill level controls.			* the 8 bits the fill level controls.
	*/			*/
	#define IG4_FIFOLVL_MASK 0x001F			#define IG4_FIFOLVL_MASK 0x01FF

	/*			/*
	* SDA_HOLD - (RW) SDA Hold Time Length Register 22.2.26			* SDA_HOLD - (RW) SDA Hold Time Length Register 22.2.26
	*			*
	* Set the SDA hold time length register in I2C clocks.			* Set the SDA hold time length register in I2C clocks.
	*/			*/
	#define IG4_SDA_HOLD_MASK 0x00FF			#define IG4_SDA_TX_HOLD_MASK 0x0000FFFF

	/*			/*
	* TX_ABRT_SOURCE- (RO) Transmit Abort Source Register 22.2.27			* TX_ABRT_SOURCE- (RO) Transmit Abort Source Register 22.2.27
	*			*
	* Indicates the cause of a transmit abort. This can indicate a			* Indicates the cause of a transmit abort. This can indicate a
	* software programming error or a device expected address width			* software programming error or a device expected address width
	* mismatch or other issues. The NORESTART conditions and GENCALL_NOACK			* mismatch or other issues. The NORESTART conditions and GENCALL_NOACK
	* can only occur if a programming error was made in the driver software.			* can only occur if a programming error was made in the driver software.
	*			*
	* In particular, it should be possible to detect whether any devices			* In particular, it should be possible to detect whether any devices
	* are on the bus by observing the GENCALL_READ status, and it might			* are on the bus by observing the GENCALL_READ status, and it might
	* be possible to detect ADDR7 vs ADDR10 mismatches.			* be possible to detect ADDR7 vs ADDR10 mismatches.
	*/			*/
	#define IG4_ABRTSRC_TRANSFER 0x00010000 /* Abort initiated by user */			#define IG4_ABRTSRC_TRANSFER 0x00010000 /* Abort initiated by user */
	#define IG4_ABRTSRC_ARBLOST 0x00001000 /* Arbitration lost */			#define IG4_ABRTSRC_ARBLOST 0x00001000 /* Arbitration lost */
	#define IG4_ABRTSRC_NORESTART_10 0x00000400 /* RESTART disabled */			#define IG4_ABRTSRC_NORESTART_10 0x00000400 /* RESTART disabled */
	#define IG4_ABRTSRC_NORESTART_START 0x00000200 /* RESTART disabled */			#define IG4_ABRTSRC_NORESTART_START 0x00000200 /* RESTART disabled */
	#define IG4_ABRTSRC_ACKED_START 0x00000080 /* Improper acked START */			#define IG4_ABRTSRC_ACKED_START 0x00000080 /* Improper acked START */
	#define IG4_ABRTSRC_GENCALL_NOACK 0x00000020 /* Improper GENCALL */			#define IG4_ABRTSRC_GENCALL_READ 0x00000020 /* Improper GENCALL */
	#define IG4_ABRTSRC_GENCALL_READ 0x00000010 /* Nobody acked GENCALL */			#define IG4_ABRTSRC_GENCALL_NOACK 0x00000010 /* Nobody acked GENCALL */
	#define IG4_ABRTSRC_TXNOACK_DATA 0x00000008 /* data phase no ACK */			#define IG4_ABRTSRC_TXNOACK_DATA 0x00000008 /* data phase no ACK */
	#define IG4_ABRTSRC_TXNOACK_ADDR10_2 0x00000004 /* addr10/1 phase no ACK */			#define IG4_ABRTSRC_TXNOACK_ADDR10_2 0x00000004 /* addr10/1 phase no ACK */
	#define IG4_ABRTSRC_TXNOACK_ADDR10_1 0x00000002 /* addr10/2 phase no ACK */			#define IG4_ABRTSRC_TXNOACK_ADDR10_1 0x00000002 /* addr10/2 phase no ACK */
	#define IG4_ABRTSRC_TXNOACK_ADDR7 0x00000001 /* addr7 phase no ACK */			#define IG4_ABRTSRC_TXNOACK_ADDR7 0x00000001 /* addr7 phase no ACK */

	/*			/*
	* SLV_DATA_NACK - (RW) Generate Slave DATA NACK Register 22.2.28			* SLV_DATA_NACK - (RW) Generate Slave DATA NACK Register 22.2.28
	*			*
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	* HCCNT_RO - Indicates that the clock timing registers are			* HCCNT_RO - Indicates that the clock timing registers are
	* RW. If not set, the registers are RO.			* RW. If not set, the registers are RO.
	* (more virtualization stuff).			* (more virtualization stuff).
	*			*
	* MAXSPEED - Indicates the maximum speed supported.			* MAXSPEED - Indicates the maximum speed supported.
	*			*
	* DATAW - Indicates the internal bus width in bits.			* DATAW - Indicates the internal bus width in bits.
	*/			*/
	#define IG4_PARAM1_TXFIFO_DEPTH(v) (((v) >> 16) & 0xFF)			#define IG4_PARAM1_TXFIFO_DEPTH(v) ((((v) >> 16) & 0xFF) + 1)
	#define IG4_PARAM1_RXFIFO_DEPTH(v) (((v) >> 8) & 0xFF)			#define IG4_PARAM1_RXFIFO_DEPTH(v) ((((v) >> 8) & 0xFF) + 1)
	#define IG4_PARAM1_CONFIG_VALID 0x00000080			#define IG4_PARAM1_CONFIG_VALID 0x00000080
	#define IG4_PARAM1_CONFIG_HASDMA 0x00000040			#define IG4_PARAM1_CONFIG_HASDMA 0x00000040
	#define IG4_PARAM1_CONFIG_INTR_IO 0x00000020			#define IG4_PARAM1_CONFIG_INTR_IO 0x00000020
	#define IG4_PARAM1_CONFIG_HCCNT_RO 0x00000010			#define IG4_PARAM1_CONFIG_HCCNT_RO 0x00000010
	#define IG4_PARAM1_CONFIG_MAXSPEED_MASK 0x0000000C			#define IG4_PARAM1_CONFIG_MAXSPEED_MASK 0x0000000C
	#define IG4_PARAM1_CONFIG_DATAW_MASK 0x00000003			#define IG4_PARAM1_CONFIG_DATAW_MASK 0x00000003

	#define IG4_CONFIG_MAXSPEED_RESERVED00 0x00000000			#define IG4_CONFIG_MAXSPEED_RESERVED00 0x00000000
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