Differential D22148 Diff 63670 sys/arm64/rockchip/clk/rk3399_cru.c

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sys/arm64/rockchip/clk/rk3399_cru.c

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#define PCLK_GPIO3 337		#define PCLK_GPIO3 337
#define PCLK_GPIO4 338		#define PCLK_GPIO4 338
#define PCLK_I2C1 341		#define PCLK_I2C1 341
#define PCLK_I2C2 342		#define PCLK_I2C2 342
#define PCLK_I2C3 343		#define PCLK_I2C3 343
#define PCLK_I2C5 344		#define PCLK_I2C5 344
#define PCLK_I2C6 345		#define PCLK_I2C6 345
#define PCLK_I2C7 346		#define PCLK_I2C7 346
		#define PCLK_SPI0 347
		#define PCLK_SPI1 348
		#define PCLK_SPI2 349
		#define PCLK_SPI4 350
		#define PCLK_SPI5 351
#define HCLK_HOST0 456		#define HCLK_HOST0 456
#define HCLK_HOST0_ARB 457		#define HCLK_HOST0_ARB 457
#define HCLK_HOST1 458		#define HCLK_HOST1 458
#define HCLK_HOST1_ARB 459		#define HCLK_HOST1_ARB 459
#define HCLK_SDMMC 462		#define HCLK_SDMMC 462

static struct rk_cru_gate rk3399_gates[] = {		static struct rk_cru_gate rk3399_gates[] = {
/* CRU_CLKGATE_CON0 */		/* CRU_CLKGATE_CON0 */
Show All 35 Lines	static struct rk_cru_gate rk3399_gates[] = {
/* CRU_CLKGATE_CON22 */		/* CRU_CLKGATE_CON22 */
CRU_GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0x358, 5)		CRU_GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0x358, 5)
CRU_GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0x358, 6)		CRU_GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0x358, 6)
CRU_GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0x358, 7)		CRU_GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0x358, 7)
CRU_GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0x358, 8)		CRU_GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0x358, 8)
CRU_GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0x358, 9)		CRU_GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0x358, 9)
CRU_GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0x358, 10)		CRU_GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0x358, 10)

		/* CRU_CLKGATE_CON23 */
		CRU_GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0x35C, 10)
		CRU_GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0x35C, 11)
		CRU_GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0x35C, 12)
		CRU_GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0x35C, 13)

/* CRU_CLKGATE_CON31 */		/* CRU_CLKGATE_CON31 */
CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0x37c, 3)		CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0x37c, 3)
CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0x37c, 4)		CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0x37c, 4)
CRU_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0x37c, 5)		CRU_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0x37c, 5)

/* CRU_CLKGATE_CON32 */		/* CRU_CLKGATE_CON32 */
CRU_GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", 0x380, 8)		CRU_GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", 0x380, 8)
CRU_GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", 0x380, 9)		CRU_GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", 0x380, 9)
CRU_GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", 0x380, 10)		CRU_GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", 0x380, 10)

/* CRU_CLKGATE_CON33 */		/* CRU_CLKGATE_CON33 */
CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0x384, 8)		CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0x384, 8)

		/* CRU_CLKGATE_CON34 */
		CRU_GATE(PCLK_SPI4, "pclk_spi5", "pclk_perilp1", 0x388, 5)
};		};


/*		/*
* PLLs		* PLLs
*/		*/

#define PLL_APLLL 1		#define PLL_APLLL 1
▲ Show 20 Lines • Show All 1,066 Lines • ▼ Show 20 Lines	static struct rk_clk_composite_def i2c7 = {
/* CRU_CLKGATE_CON10 */		/* CRU_CLKGATE_CON10 */
.gate_offset = 0x0328,		.gate_offset = 0x0328,
.gate_shift = 5,		.gate_shift = 5,

.flags = RK_CLK_COMPOSITE_HAVE_MUX \| RK_CLK_COMPOSITE_HAVE_GATE,		.flags = RK_CLK_COMPOSITE_HAVE_MUX \| RK_CLK_COMPOSITE_HAVE_GATE,
};		};

/*		/*
		* spi
		*/
		static const char *spi_parents[] = {"cpll", "gpll"};

		#define SCLK_SPI0 71
		#define SCLK_SPI1 72
		#define SCLK_SPI2 73
		#define SCLK_SPI4 74
		#define SCLK_SPI5 75

		static struct rk_clk_composite_def spi0 = {
		.clkdef = {
		.id = SCLK_SPI0,
		.name = "clk_spi0",
		.parent_names = spi_parents,
		.parent_cnt = nitems(spi_parents),
		},
		/* CRU_CLKSEL_CON59 */
		.muxdiv_offset = 0x01ec,
		.mux_shift = 7,
		.mux_width = 1,

		.div_shift = 0,
		.div_width = 7,

		/* CRU_CLKGATE_CON9 */
		.gate_offset = 0x0324,
		.gate_shift = 12,

		.flags = RK_CLK_COMPOSITE_HAVE_MUX \| RK_CLK_COMPOSITE_HAVE_GATE,
		};

		static struct rk_clk_composite_def spi1 = {
		.clkdef = {
		.id = SCLK_SPI1,
		.name = "clk_spi1",
		.parent_names = spi_parents,
		.parent_cnt = nitems(spi_parents),
		},
		/* CRU_CLKSEL_CON59 */
		.muxdiv_offset = 0x01ec,
		.mux_shift = 15,
		.mux_width = 1,

		.div_shift = 8,
		.div_width = 7,

		/* CRU_CLKGATE_CON9 */
		.gate_offset = 0x0324,
		.gate_shift = 13,

		.flags = RK_CLK_COMPOSITE_HAVE_MUX \| RK_CLK_COMPOSITE_HAVE_GATE,
		};

		static struct rk_clk_composite_def spi2 = {
		.clkdef = {
		.id = SCLK_SPI2,
		.name = "clk_spi2",
		.parent_names = spi_parents,
		.parent_cnt = nitems(spi_parents),
		},
		/* CRU_CLKSEL_CON60 */
		.muxdiv_offset = 0x01f0,
		.mux_shift = 7,
		.mux_width = 1,

		.div_shift = 0,
		.div_width = 7,

		/* CRU_CLKGATE_CON9 */
		.gate_offset = 0x0324,
		.gate_shift = 14,

		.flags = RK_CLK_COMPOSITE_HAVE_MUX \| RK_CLK_COMPOSITE_HAVE_GATE,
		};

		static struct rk_clk_composite_def spi4 = {
		.clkdef = {
		.id = SCLK_SPI4,
		.name = "clk_spi4",
		.parent_names = spi_parents,
		.parent_cnt = nitems(spi_parents),
		},
		/* CRU_CLKSEL_CON60 */
		.muxdiv_offset = 0x01f0,
		.mux_shift = 15,
		.mux_width = 1,

		.div_shift = 8,
		.div_width = 7,

		/* CRU_CLKGATE_CON9 */
		.gate_offset = 0x0324,
		.gate_shift = 15,

		.flags = RK_CLK_COMPOSITE_HAVE_MUX \| RK_CLK_COMPOSITE_HAVE_GATE,
		};

		static struct rk_clk_composite_def spi5 = {
		.clkdef = {
		.id = SCLK_SPI5,
		.name = "clk_spi5",
		.parent_names = spi_parents,
		.parent_cnt = nitems(spi_parents),
		},
		/* CRU_CLKSEL_CON58 */
		.muxdiv_offset = 0x01e8,
		.mux_shift = 15,
		.mux_width = 1,

		.div_shift = 8,
		.div_width = 7,

		/* CRU_CLKGATE_CON13 */
		.gate_offset = 0x0334,
		.gate_shift = 13,

		.flags = RK_CLK_COMPOSITE_HAVE_MUX \| RK_CLK_COMPOSITE_HAVE_GATE,
		};

		/*
* ARM CPU clocks (LITTLE and big)		* ARM CPU clocks (LITTLE and big)
*/		*/
#define ARMCLKL 8		#define ARMCLKL 8
#define ARMCLKB 9		#define ARMCLKB 9

static const char *armclk_parents[] = {"lpll", "bpll", "dpll", "gpll"};		static const char *armclk_parents[] = {"lpll", "bpll", "dpll", "gpll"};

static struct rk_clk_armclk_rates rk3399_armclkl_rates[] = {		static struct rk_clk_armclk_rates rk3399_armclkl_rates[] = {
▲ Show 20 Lines • Show All 222 Lines • ▼ Show 20 Lines	static struct rk_clk_composite_def hclk_sd = {
.gate_shift = 13,		.gate_shift = 13,

.flags = RK_CLK_COMPOSITE_HAVE_MUX \| RK_CLK_COMPOSITE_HAVE_GATE,		.flags = RK_CLK_COMPOSITE_HAVE_MUX \| RK_CLK_COMPOSITE_HAVE_GATE,
};		};

#define SCLK_SDMMC 76		#define SCLK_SDMMC 76

static const char *sclk_sdmmc_parents[] = {"cpll", "gpll", "npll", "ppll"};		static const char *sclk_sdmmc_parents[] = {"cpll", "gpll", "npll", "ppll"};

		manuUnsubmitted Done Inline Actions hack leftovers. manu: hack leftovers.
static struct rk_clk_composite_def sclk_sdmmc = {		static struct rk_clk_composite_def sclk_sdmmc = {
.clkdef = {		.clkdef = {
.id = SCLK_SDMMC,		.id = SCLK_SDMMC,
.name = "sclk_sdmmc",		.name = "sclk_sdmmc",
.parent_names = sclk_sdmmc_parents,		.parent_names = sclk_sdmmc_parents,
.parent_cnt = nitems(sclk_sdmmc_parents),		.parent_cnt = nitems(sclk_sdmmc_parents),
},		},

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/*		/*
* emmc		* emmc
*/		*/

#define SCLK_EMMC 78		#define SCLK_EMMC 78

static const char *sclk_emmc_parents[] = {"cpll", "gpll", "npll"};		static const char *sclk_emmc_parents[] = {"cpll", "gpll", "npll"};

static struct rk_clk_composite_def sclk_emmc = {		static struct rk_clk_composite_def sclk_emmc = {
		manuUnsubmitted Done Inline Actions hack leftovers. manu: hack leftovers.
.clkdef = {		.clkdef = {
.id = SCLK_EMMC,		.id = SCLK_EMMC,
.name = "sclk_emmc",		.name = "sclk_emmc",
.parent_names = sclk_emmc_parents,		.parent_names = sclk_emmc_parents,
.parent_cnt = nitems(sclk_emmc_parents),		.parent_cnt = nitems(sclk_emmc_parents),
},		},

.muxdiv_offset = 0x158,		.muxdiv_offset = 0x158,
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines	static struct rk_clk rk3399_clks[] = {
{		{
.type = RK_CLK_COMPOSITE,		.type = RK_CLK_COMPOSITE,
.clk.composite = &i2c6,		.clk.composite = &i2c6,
},		},
{		{
.type = RK_CLK_COMPOSITE,		.type = RK_CLK_COMPOSITE,
.clk.composite = &i2c7,		.clk.composite = &i2c7,
},		},
		{
		.type = RK_CLK_COMPOSITE,
		.clk.composite = &spi0,
		},
		{
		.type = RK_CLK_COMPOSITE,
		.clk.composite = &spi1,
		},
		{
		.type = RK_CLK_COMPOSITE,
		.clk.composite = &spi2,
		},
		{
		.type = RK_CLK_COMPOSITE,
		.clk.composite = &spi4,
		},
		{
		.type = RK_CLK_COMPOSITE,
		.clk.composite = &spi5,
		},
{		{
.type = RK_CLK_ARMCLK,		.type = RK_CLK_ARMCLK,
.clk.armclk = &armclk_l,		.clk.armclk = &armclk_l,
},		},
{		{
.type = RK_CLK_ARMCLK,		.type = RK_CLK_ARMCLK,
.clk.armclk = &armclk_b,		.clk.armclk = &armclk_b,
},		},
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