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sys/dev/ichiic/ig4_pci.c
| Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines | |||||
| #define PCI_CHIP_APL_I2C_0 0x5aac8086 | #define PCI_CHIP_APL_I2C_0 0x5aac8086 | ||||
| #define PCI_CHIP_APL_I2C_1 0x5aae8086 | #define PCI_CHIP_APL_I2C_1 0x5aae8086 | ||||
| #define PCI_CHIP_APL_I2C_2 0x5ab08086 | #define PCI_CHIP_APL_I2C_2 0x5ab08086 | ||||
| #define PCI_CHIP_APL_I2C_3 0x5ab28086 | #define PCI_CHIP_APL_I2C_3 0x5ab28086 | ||||
| #define PCI_CHIP_APL_I2C_4 0x5ab48086 | #define PCI_CHIP_APL_I2C_4 0x5ab48086 | ||||
| #define PCI_CHIP_APL_I2C_5 0x5ab68086 | #define PCI_CHIP_APL_I2C_5 0x5ab68086 | ||||
| #define PCI_CHIP_APL_I2C_6 0x5ab88086 | #define PCI_CHIP_APL_I2C_6 0x5ab88086 | ||||
| #define PCI_CHIP_APL_I2C_7 0x5aba8086 | #define PCI_CHIP_APL_I2C_7 0x5aba8086 | ||||
| #define PCI_CHIP_CANNONLAKE_LP_I2C_0 0x9dc58086 | |||||
| #define PCI_CHIP_CANNONLAKE_LP_I2C_1 0x9dc68086 | |||||
| #define PCI_CHIP_CANNONLAKE_LP_I2C_2 0x9de88086 | |||||
| #define PCI_CHIP_CANNONLAKE_LP_I2C_3 0x9de98086 | |||||
| #define PCI_CHIP_CANNONLAKE_LP_I2C_4 0x9dea8086 | |||||
| #define PCI_CHIP_CANNONLAKE_LP_I2C_5 0x9deb8086 | |||||
| #define PCI_CHIP_CANNONLAKE_H_I2C_0 0xa3688086 | |||||
| #define PCI_CHIP_CANNONLAKE_H_I2C_1 0xa3698086 | |||||
| #define PCI_CHIP_CANNONLAKE_H_I2C_2 0xa36a8086 | |||||
| #define PCI_CHIP_CANNONLAKE_H_I2C_3 0xa36b8086 | |||||
| struct ig4iic_pci_device { | struct ig4iic_pci_device { | ||||
| uint32_t devid; | uint32_t devid; | ||||
| const char *desc; | const char *desc; | ||||
| enum ig4_vers version; | enum ig4_vers version; | ||||
| }; | }; | ||||
| static struct ig4iic_pci_device ig4iic_pci_devices[] = { | static struct ig4iic_pci_device ig4iic_pci_devices[] = { | ||||
| Show All 15 Lines | static struct ig4iic_pci_device ig4iic_pci_devices[] = { | ||||
| { PCI_CHIP_KABYLAKE_I2C_1, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE}, | { PCI_CHIP_KABYLAKE_I2C_1, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE}, | ||||
| { PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL}, | { PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL}, | ||||
| { PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL}, | { PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL}, | ||||
| { PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL}, | { PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL}, | ||||
| { PCI_CHIP_APL_I2C_3, "Intel Apollo Lake I2C Controller-3", IG4_APL}, | { PCI_CHIP_APL_I2C_3, "Intel Apollo Lake I2C Controller-3", IG4_APL}, | ||||
| { PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_APL}, | { PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_APL}, | ||||
| { PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_APL}, | { PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_APL}, | ||||
| { PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_APL}, | { PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_APL}, | ||||
| { PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL} | { PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL}, | ||||
| { PCI_CHIP_CANNONLAKE_LP_I2C_0, "Intel Cannon Lake-LP I2C Controller-0", IG4_CANNONLAKE}, | |||||
| { PCI_CHIP_CANNONLAKE_LP_I2C_1, "Intel Cannon Lake-LP I2C Controller-1", IG4_CANNONLAKE}, | |||||
| { PCI_CHIP_CANNONLAKE_LP_I2C_2, "Intel Cannon Lake-LP I2C Controller-2", IG4_CANNONLAKE}, | |||||
| { PCI_CHIP_CANNONLAKE_LP_I2C_3, "Intel Cannon Lake-LP I2C Controller-3", IG4_CANNONLAKE}, | |||||
| { PCI_CHIP_CANNONLAKE_LP_I2C_4, "Intel Cannon Lake-LP I2C Controller-4", IG4_CANNONLAKE}, | |||||
| { PCI_CHIP_CANNONLAKE_LP_I2C_5, "Intel Cannon Lake-LP I2C Controller-5", IG4_CANNONLAKE}, | |||||
| { PCI_CHIP_CANNONLAKE_H_I2C_0, "Intel Cannon Lake-H I2C Controller-0", IG4_CANNONLAKE}, | |||||
| { PCI_CHIP_CANNONLAKE_H_I2C_1, "Intel Cannon Lake-H I2C Controller-1", IG4_CANNONLAKE}, | |||||
| { PCI_CHIP_CANNONLAKE_H_I2C_2, "Intel Cannon Lake-H I2C Controller-2", IG4_CANNONLAKE}, | |||||
| { PCI_CHIP_CANNONLAKE_H_I2C_3, "Intel Cannon Lake-H I2C Controller-3", IG4_CANNONLAKE}, | |||||
| }; | }; | ||||
| static int | static int | ||||
| ig4iic_pci_probe(device_t dev) | ig4iic_pci_probe(device_t dev) | ||||
| { | { | ||||
| ig4iic_softc_t *sc = device_get_softc(dev); | ig4iic_softc_t *sc = device_get_softc(dev); | ||||
| uint32_t devid; | uint32_t devid; | ||||
| int i; | int i; | ||||
| ▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines | if (sc->regs_res) { | ||||
| bus_release_resource(dev, SYS_RES_MEMORY, | bus_release_resource(dev, SYS_RES_MEMORY, | ||||
| sc->regs_rid, sc->regs_res); | sc->regs_rid, sc->regs_res); | ||||
| sc->regs_res = NULL; | sc->regs_res = NULL; | ||||
| } | } | ||||
| return (0); | return (0); | ||||
| } | } | ||||
| static int | |||||
| ig4iic_pci_suspend(device_t dev) | |||||
| { | |||||
| ig4iic_softc_t *sc = device_get_softc(dev); | |||||
| return (ig4iic_suspend(sc)); | |||||
| } | |||||
| static int | |||||
| ig4iic_pci_resume(device_t dev) | |||||
| { | |||||
| ig4iic_softc_t *sc = device_get_softc(dev); | |||||
| return (ig4iic_resume(sc)); | |||||
| } | |||||
| static device_method_t ig4iic_pci_methods[] = { | static device_method_t ig4iic_pci_methods[] = { | ||||
| /* Device interface */ | /* Device interface */ | ||||
| DEVMETHOD(device_probe, ig4iic_pci_probe), | DEVMETHOD(device_probe, ig4iic_pci_probe), | ||||
| DEVMETHOD(device_attach, ig4iic_pci_attach), | DEVMETHOD(device_attach, ig4iic_pci_attach), | ||||
| DEVMETHOD(device_detach, ig4iic_pci_detach), | DEVMETHOD(device_detach, ig4iic_pci_detach), | ||||
| DEVMETHOD(device_suspend, ig4iic_pci_suspend), | |||||
| DEVMETHOD(device_resume, ig4iic_pci_resume), | |||||
| /* Bus interface */ | |||||
| DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), | |||||
| DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), | |||||
| DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), | |||||
| DEVMETHOD(bus_release_resource, bus_generic_release_resource), | |||||
| DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), | |||||
| DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), | |||||
| DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), | |||||
| DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), | |||||
| DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), | |||||
| /* iicbus interface */ | |||||
| DEVMETHOD(iicbus_transfer, ig4iic_transfer), | DEVMETHOD(iicbus_transfer, ig4iic_transfer), | ||||
| DEVMETHOD(iicbus_reset, ig4iic_reset), | DEVMETHOD(iicbus_reset, ig4iic_reset), | ||||
| DEVMETHOD(iicbus_callback, iicbus_null_callback), | DEVMETHOD(iicbus_callback, ig4iic_callback), | ||||
| DEVMETHOD_END | DEVMETHOD_END | ||||
| }; | }; | ||||
| static driver_t ig4iic_pci_driver = { | static driver_t ig4iic_pci_driver = { | ||||
| "ig4iic_pci", | "ig4iic", | ||||
| ig4iic_pci_methods, | ig4iic_pci_methods, | ||||
| sizeof(struct ig4iic_softc) | sizeof(struct ig4iic_softc) | ||||
| }; | }; | ||||
| static devclass_t ig4iic_pci_devclass; | DRIVER_MODULE_ORDERED(ig4iic, pci, ig4iic_pci_driver, ig4iic_devclass, 0, 0, | ||||
| DRIVER_MODULE_ORDERED(ig4iic_pci, pci, ig4iic_pci_driver, ig4iic_pci_devclass, 0, 0, | |||||
| SI_ORDER_ANY); | SI_ORDER_ANY); | ||||
| MODULE_DEPEND(ig4iic_pci, pci, 1, 1, 1); | MODULE_DEPEND(ig4iic, pci, 1, 1, 1); | ||||
| MODULE_DEPEND(ig4iic_pci, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); | MODULE_PNP_INFO("W32:vendor/device", pci, ig4iic, ig4iic_pci_devices, | ||||
| MODULE_VERSION(ig4iic_pci, 1); | |||||
| MODULE_PNP_INFO("W32:vendor/device", pci, ig4iic_pci, ig4iic_pci_devices, | |||||
| nitems(ig4iic_pci_devices)); | nitems(ig4iic_pci_devices)); | ||||