Differential D22016 Diff 63241 sys/dev/ichiic/ig4_iic.c

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sys/dev/ichiic/ig4_iic.c

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/*		/*
* Intel fourth generation mobile cpus integrated I2C device.		* Intel fourth generation mobile cpus integrated I2C device.
*		*
* See ig4_reg.h for datasheet reference and notes.		* See ig4_reg.h for datasheet reference and notes.
* See ig4_var.h for locking semantics.		* See ig4_var.h for locking semantics.
*/		*/

		#include "opt_acpi.h"

#include <sys/param.h>		#include <sys/param.h>
#include <sys/systm.h>		#include <sys/systm.h>
#include <sys/kernel.h>		#include <sys/kernel.h>
#include <sys/module.h>		#include <sys/module.h>
#include <sys/errno.h>		#include <sys/errno.h>
		#include <sys/kdb.h>
#include <sys/lock.h>		#include <sys/lock.h>
#include <sys/mutex.h>		#include <sys/mutex.h>
		#include <sys/proc.h>
#include <sys/sx.h>		#include <sys/sx.h>
#include <sys/syslog.h>		#include <sys/syslog.h>
#include <sys/bus.h>		#include <sys/bus.h>
#include <sys/sysctl.h>		#include <sys/sysctl.h>

#include <machine/bus.h>		#include <machine/bus.h>
#include <sys/rman.h>		#include <sys/rman.h>

#include <dev/pci/pcivar.h>		#ifdef DEV_ACPI
#include <dev/pci/pcireg.h>		#include <contrib/dev/acpica/include/acpi.h>
		#include <contrib/dev/acpica/include/accommon.h>
		#include <dev/acpica/acpivar.h>
		#endif

#include <dev/iicbus/iicbus.h>		#include <dev/iicbus/iicbus.h>
#include <dev/iicbus/iiconf.h>		#include <dev/iicbus/iiconf.h>

#include <dev/ichiic/ig4_reg.h>		#include <dev/ichiic/ig4_reg.h>
#include <dev/ichiic/ig4_var.h>		#include <dev/ichiic/ig4_var.h>

#define TRANS_NORMAL 1		#define DO_POLL(sc) (cold \|\| kdb_active \|\| SCHEDULER_STOPPED() \|\| sc->poll)
#define TRANS_PCALL 2
#define TRANS_BLOCK 3

static void ig4iic_start(void *xdev);		/*
		* Clock register values calculation formulas and timings are snarfed from
		* Linux driver.
		* S_SCL_HCNT = IC clock rate (tHIGH + SDA falling time) - 3
		* S_SCL_LCNT = IC clock rate (tLOW + SCL falling time) - 1
		* SDA_TX_HOLD = IC clock rate * SDA hold time
		* All results are rounded to nearest.
		*
		* tLOW and tHIGH periods of the SCL clock are taken from I2C specification:
		* Speed mode STD FAST FAST+ HIGH
		* tHIGH 4.0 ns 0.6 ns 0.26 ns 0.06-0.12 ns
		* tLOW 4.7 ns 1.3 ns 0.5 ns 0.16-0.32 ns
		*
		* HIGH Speed mode tHIGH/tLOW values are depend on bus capacitance.
		*/
		static const struct ig4_cfg ig4iic_configs[] = {
		[IG4_HASWELL] = {
		.bus_speed = IG4_CTL_SPEED_FAST,
		.ss_scl_hcnt = 432,
		impUnsubmitted Done Inline Actions Is there some way that these can be calculated rather than being magic numbers? Here and below... imp: Is there some way that these can be calculated rather than being magic numbers? Here and below..
		wulfAuthorUnsubmitted Done Inline Actions Clock registers values are now calculated based on I2C protocol timing constraints and IC parameters taken from LPSS driver. Latter are still kind of magic numbers, but they are physical parameters at least. wulf: Clock registers values are now calculated based on I2C protocol timing constraints and IC…
		.ss_scl_lcnt = 507,
		.fs_scl_hcnt = 110,
		.fs_scl_lcnt = 160,
		.sda_tx_hold = 9,
		.txfifo_depth = 32,
		.rxfifo_depth = 32,
		},
		[IG4_ATOM] = {
		.bus_speed = IG4_CTL_SPEED_FAST,
		.ss_scl_hcnt = 512,
		.ss_scl_lcnt = 512,
		.fs_scl_hcnt = 85,
		.fs_scl_lcnt = 153,
		.sda_tx_hold = 6,
		.txfifo_depth = 32,
		.rxfifo_depth = 32,
		},
		[IG4_SKYLAKE] = {
		/*
		* IC clock rate: 120 MHz
		* SDA hold time: 230 ns
		* SDA falling time: 300 ns
		* SCL falling time: 300 ns
		*/
		.bus_speed = IG4_CTL_SPEED_FAST,
		.ss_scl_hcnt = 513,
		.ss_scl_lcnt = 599,
		.fs_scl_hcnt = 105,
		.fs_scl_lcnt = 191,
		.sda_tx_hold = 28,
		.txfifo_depth = 64,
		.rxfifo_depth = 64,
		},
		[IG4_APL] = {
		/*
		* IC clock rate: 133 MHz
		* SDA hold time: 207 ns
		* SDA falling time: 171 ns
		* SCL falling time: 208 ns
		*/
		.bus_speed = IG4_CTL_SPEED_FAST,
		.ss_scl_hcnt = 552,
		.ss_scl_lcnt = 652,
		.fs_scl_hcnt = 100,
		.fs_scl_lcnt = 200,
		.sda_tx_hold = 28,
		},
		[IG4_CANNONLAKE] = {
		/*
		* IC clock rate: 216 MHz
		* SDA hold time: 230 ns
		* SDA falling time: 300 ns
		* SCL falling time: 300 ns
		*/
		.bus_speed = IG4_CTL_SPEED_FAST,
		.ss_scl_hcnt = 926,
		.ss_scl_lcnt = 1079,
		.fs_scl_hcnt = 192,
		.fs_scl_lcnt = 345,
		.sda_tx_hold = 50,
		.txfifo_depth = 64,
		.rxfifo_depth = 64,
		},
		};

		static int ig4iic_set_config(ig4iic_softc_t *sc, bool reset);
static void ig4iic_intr(void *cookie);		static void ig4iic_intr(void *cookie);
static void ig4iic_dump(ig4iic_softc_t *sc);		static void ig4iic_dump(ig4iic_softc_t *sc);

static int ig4_dump;		static int ig4_dump;
SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLFLAG_RW,		SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLFLAG_RW,
&ig4_dump, 0, "Dump controller registers");		&ig4_dump, 0, "Dump controller registers");

		static int ig4_timings;
		SYSCTL_INT(_debug, OID_AUTO, ig4_timings, CTLFLAG_RDTUN, &ig4_timings, 0,
		"Controller timings 0=ACPI, 1=predefined, 2=legacy, 3=do not change");

/*		/*
* Low-level inline support functions		* Low-level inline support functions
*/		*/
static __inline void		static __inline void
reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value)		reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value)
{		{
bus_write_4(sc->regs_res, reg, value);		bus_write_4(sc->regs_res, reg, value);
bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE);		bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE);
}		}

static __inline uint32_t		static __inline uint32_t
reg_read(ig4iic_softc_t *sc, uint32_t reg)		reg_read(ig4iic_softc_t *sc, uint32_t reg)
{		{
uint32_t value;		uint32_t value;

bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_READ);		bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_READ);
value = bus_read_4(sc->regs_res, reg);		value = bus_read_4(sc->regs_res, reg);
return (value);		return (value);
}		}

		static void
		set_intr_mask(ig4iic_softc_t *sc, uint32_t val)
		{
		if (sc->intr_mask != val) {
		reg_write(sc, IG4_REG_INTR_MASK, val);
		impUnsubmitted Done Inline Actions Why do you need to track this and not set it to the same value? Seems like a good place for a comment. imp: Why do you need to track this and not set it to the same value? Seems like a good place for a…
		wulfAuthorUnsubmitted Done Inline Actions It is just microoptimization inherited from DragonflyBSD change. This part can be done in slightly better way, without tracking for the same value, but at a cost of source diverging. wulf: It is just microoptimization inherited from DragonflyBSD change. This part can be done in…
		sc->intr_mask = val;
		}
		}

		static int
		intrstat2iic(ig4iic_softc_t *sc, uint32_t val)
		{
		uint32_t src;

		if (val & IG4_INTR_RX_UNDER)
		reg_read(sc, IG4_REG_CLR_RX_UNDER);
		if (val & IG4_INTR_RX_OVER)
		reg_read(sc, IG4_REG_CLR_RX_OVER);
		if (val & IG4_INTR_TX_OVER)
		reg_read(sc, IG4_REG_CLR_TX_OVER);

		if (val & IG4_INTR_TX_ABRT) {
		src = reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
		reg_read(sc, IG4_REG_CLR_TX_ABORT);
		/* User-requested abort. Not really a error */
		if (src & IG4_ABRTSRC_TRANSFER)
		return (IIC_ESTATUS);
		/* Master has lost arbitration */
		if (src & IG4_ABRTSRC_ARBLOST)
		return (IIC_EBUSBSY);
		/* Did not receive an acknowledge from the remote slave */
		if (src & (IG4_ABRTSRC_TXNOACK_ADDR7 \|
		IG4_ABRTSRC_TXNOACK_ADDR10_1 \|
		IG4_ABRTSRC_TXNOACK_ADDR10_2 \|
		IG4_ABRTSRC_TXNOACK_DATA \|
		IG4_ABRTSRC_GENCALL_NOACK))
		return (IIC_ENOACK);
		/* Programming errors */
		if (src & (IG4_ABRTSRC_GENCALL_READ \|
		IG4_ABRTSRC_NORESTART_START \|
		IG4_ABRTSRC_NORESTART_10))
		return (IIC_ENOTSUPP);
		/* Other errors */
		if (src & IG4_ABRTSRC_ACKED_START)
		return (IIC_EBUSERR);
		}
/*		/*
		* TX_OVER, RX_OVER and RX_UNDER are caused by wrong RX/TX FIFO depth
		* detection or driver's read/write pipelining errors.
		*/
		if (val & (IG4_INTR_TX_OVER \| IG4_INTR_RX_OVER))
		return (IIC_EOVERFLOW);
		if (val & IG4_INTR_RX_UNDER)
		return (IIC_EUNDERFLOW);

		return (IIC_NOERR);
		}

		/*
* Enable or disable the controller and wait for the controller to acknowledge		* Enable or disable the controller and wait for the controller to acknowledge
* the state change.		* the state change.
*/		*/
static int		static int
set_controller(ig4iic_softc_t *sc, uint32_t ctl)		set_controller(ig4iic_softc_t *sc, uint32_t ctl)
{		{
int retry;		int retry;
int error;		int error;
uint32_t v;		uint32_t v;

/*		/*
* When the controller is enabled, interrupt on STOP detect		* When the controller is enabled, interrupt on STOP detect
* or receive character ready and clear pending interrupts.		* or receive character ready and clear pending interrupts.
*/		*/
if (ctl & IG4_I2C_ENABLE) {		set_intr_mask(sc, 0);
reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET \|		if (ctl & IG4_I2C_ENABLE)
IG4_INTR_RX_FULL);
reg_read(sc, IG4_REG_CLR_INTR);		reg_read(sc, IG4_REG_CLR_INTR);
} else
reg_write(sc, IG4_REG_INTR_MASK, 0);

reg_write(sc, IG4_REG_I2C_EN, ctl);		reg_write(sc, IG4_REG_I2C_EN, ctl);
error = IIC_ETIMEOUT;		error = IIC_ETIMEOUT;

for (retry = 100; retry > 0; --retry) {		for (retry = 100; retry > 0; --retry) {
v = reg_read(sc, IG4_REG_ENABLE_STATUS);		v = reg_read(sc, IG4_REG_ENABLE_STATUS);
if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) {		if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) {
error = 0;		error = 0;
break;		break;
}		}
if (cold)		pause("i2cslv", 1);
DELAY(1000);
else
mtx_sleep(sc, &sc->io_lock, 0, "i2cslv", 1);
}		}
return (error);		return (error);
}		}

/*		/*
* Wait up to 25ms for the requested status using a 25uS polling loop.		* Wait up to 25ms for the requested interrupt using a 25uS polling loop.
*/		*/
static int		static int
wait_status(ig4iic_softc_t *sc, uint32_t status)		wait_intr(ig4iic_softc_t *sc, uint32_t intr)
{		{
uint32_t v;		uint32_t v;
int error;		int error;
int txlvl = -1;		int txlvl = -1;
u_int count_us = 0;		u_int count_us = 0;
u_int limit_us = 25000; /* 25ms */		u_int limit_us = 25000; /* 25ms */

error = IIC_ETIMEOUT;		error = IIC_ETIMEOUT;

for (;;) {		while (error == IIC_ETIMEOUT) {
/*		/*
* Check requested status		* Check requested status
*/		*/
v = reg_read(sc, IG4_REG_I2C_STA);		v = reg_read(sc, IG4_REG_RAW_INTR_STAT);
if (v & status) {		error = intrstat2iic(sc, v & IG4_INTR_ERR_MASK);
error = 0;		if (error)
break;		break;
}

/*		if (v & intr) {
* When waiting for receive data break-out if the interrupt
* loaded data into the FIFO.
*/
if (status & IG4_STATUS_RX_NOTEMPTY) {
if (sc->rpos != sc->rnext) {
error = 0;		error = 0;
break;		break;
}		}
}

/*		/*
* When waiting for the transmit FIFO to become empty,		* When waiting for the transmit FIFO to become empty,
* reset the timeout if we see a change in the transmit		* reset the timeout if we see a change in the transmit
* FIFO level as progress is being made.		* FIFO level as progress is being made.
*/		*/
if (status & IG4_STATUS_TX_EMPTY) {		if (intr & (IG4_INTR_TX_EMPTY \| IG4_INTR_STOP_DET)) {
v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK;		v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK;
if (txlvl != v) {		if (txlvl != v) {
txlvl = v;		txlvl = v;
count_us = 0;		count_us = 0;
}		}
}		}

/*		/*
* Stop if we've run out of time.		* Stop if we've run out of time.
*/		*/
if (count_us >= limit_us)		if (count_us >= limit_us) {
		error = IIC_ETIMEOUT;
break;		break;
		}

/*		/*
* When waiting for receive data let the interrupt do its		* When polling is not requested let the interrupt do its work.
* work, otherwise poll with the lock held.
*/		*/
if (status & IG4_STATUS_RX_NOTEMPTY) {		if (!DO_POLL(sc)) {
mtx_sleep(sc, &sc->io_lock, 0, "i2cwait",		mtx_lock(&sc->io_lock);
		sc->error = 0;
		set_intr_mask(sc, intr \| IG4_INTR_ERR_MASK);
		error = mtx_sleep(sc, &sc->io_lock, 0, "i2cwait",
(hz + 99) / 100); /* sleep up to 10ms */		(hz + 99) / 100); /* sleep up to 10ms */
		if (error != 0)
		error = IIC_ETIMEOUT;
		else
		error = sc->error;
		set_intr_mask(sc, 0);
		mtx_unlock(&sc->io_lock);
count_us += 10000;		count_us += 10000;
} else {		} else {
DELAY(25);		DELAY(25);
count_us += 25;		count_us += 25;
		error = IIC_ETIMEOUT;
}		}
}		}

return (error);		return (error);
}		}

/*		/*
* Read I2C data. The data might have already been read by
* the interrupt code, otherwise it is sitting in the data
* register.
*/
static uint8_t
data_read(ig4iic_softc_t *sc)
{
uint8_t c;

if (sc->rpos == sc->rnext) {
c = (uint8_t)reg_read(sc, IG4_REG_DATA_CMD);
} else {
c = sc->rbuf[sc->rpos & IG4_RBUFMASK];
++sc->rpos;
}
return (c);
}

/*
* Set the slave address. The controller must be disabled when		* Set the slave address. The controller must be disabled when
* changing the address.		* changing the address.
*		*
* This operation does not issue anything to the I2C bus but sets		* This operation does not issue anything to the I2C bus but sets
* the target address for when the controller later issues a START.		* the target address for when the controller later issues a START.
*/		*/
static void		static void
set_slave_addr(ig4iic_softc_t *sc, uint8_t slave)		set_slave_addr(ig4iic_softc_t *sc, uint8_t slave)
{		{
uint32_t tar;		uint32_t tar;
uint32_t ctl;		uint32_t ctl;
int use_10bit;		int use_10bit;

use_10bit = 0;		use_10bit = 0;
if (sc->slave_valid && sc->last_slave == slave &&		if (sc->slave_valid && sc->last_slave == slave &&
sc->use_10bit == use_10bit) {		sc->use_10bit == use_10bit) {
return;		return;
}		}
sc->use_10bit = use_10bit;		sc->use_10bit = use_10bit;

/*		/*
* Wait for TXFIFO to drain before disabling the controller.		* Wait for TXFIFO to drain before disabling the controller.
*
* If a write message has not been completed it's really a
* programming error, but for now in that case issue an extra
* byte + STOP.
*
* If a read message has not been completed it's also a programming
* error, for now just ignore it.
*/		*/
wait_status(sc, IG4_STATUS_TX_NOTFULL);		wait_intr(sc, IG4_INTR_TX_EMPTY);
if (sc->write_started) {
reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_STOP);
sc->write_started = 0;
}
if (sc->read_started)
sc->read_started = 0;
wait_status(sc, IG4_STATUS_TX_EMPTY);

set_controller(sc, 0);		set_controller(sc, 0);
ctl = reg_read(sc, IG4_REG_CTL);		ctl = reg_read(sc, IG4_REG_CTL);
ctl &= ~IG4_CTL_10BIT;		ctl &= ~IG4_CTL_10BIT;
ctl \|= IG4_CTL_RESTARTEN;		ctl \|= IG4_CTL_RESTARTEN;

tar = slave;		tar = slave;
if (sc->use_10bit) {		if (sc->use_10bit) {
tar \|= IG4_TAR_10BIT;		tar \|= IG4_TAR_10BIT;
ctl \|= IG4_CTL_10BIT;		ctl \|= IG4_CTL_10BIT;
}		}
reg_write(sc, IG4_REG_CTL, ctl);		reg_write(sc, IG4_REG_CTL, ctl);
reg_write(sc, IG4_REG_TAR_ADD, tar);		reg_write(sc, IG4_REG_TAR_ADD, tar);
set_controller(sc, IG4_I2C_ENABLE);		set_controller(sc, IG4_I2C_ENABLE);
sc->slave_valid = 1;		sc->slave_valid = 1;
sc->last_slave = slave;		sc->last_slave = slave;
}		}

/*		/*
* IICBUS API FUNCTIONS		* IICBUS API FUNCTIONS
*/		*/
static int		static int
ig4iic_xfer_start(ig4iic_softc_t *sc, uint16_t slave)		ig4iic_xfer_start(ig4iic_softc_t *sc, uint16_t slave, bool repeated_start)
{		{
set_slave_addr(sc, slave >> 1);		set_slave_addr(sc, slave >> 1);

		if (!repeated_start) {
		/*
		* Clear any previous TX/RX FIFOs overflow/underflow bits
		* and I2C bus STOP condition.
		*/
		reg_read(sc, IG4_REG_CLR_INTR);
		}

return (0);		return (0);
}		}

		static bool
		ig4iic_xfer_is_started(ig4iic_softc_t *sc)
		{
		/*
		* It requires that no IG4_REG_CLR_INTR or IG4_REG_CLR_START/STOP_DET
		* register reads is issued after START condition.
		*/
		return ((reg_read(sc, IG4_REG_RAW_INTR_STAT) &
		(IG4_INTR_START_DET \| IG4_INTR_STOP_DET)) == IG4_INTR_START_DET);
		}

static int		static int
		ig4iic_xfer_abort(ig4iic_softc_t *sc)
		{
		int error;

		/* Request send of STOP condition and flush of TX FIFO */
		set_controller(sc, IG4_I2C_ABORT \| IG4_I2C_ENABLE);
		/*
		* Wait for the TX_ABRT interrupt with ABRTSRC_TRANSFER
		* bit set in TX_ABRT_SOURCE register.
		*/
		error = wait_intr(sc, IG4_INTR_STOP_DET);
		set_controller(sc, IG4_I2C_ENABLE);

		return (error == IIC_ESTATUS ? 0 : error);
		}

		/*
		* Amount of unread data before next burst to get better I2C bus utilization.
		* 2 bytes is enough in FAST mode. 8 bytes is better in FAST+ and HIGH modes.
		* Intel-recommended value is 16 for DMA transfers with 64-byte depth FIFOs.
		*/
		#define IG4_FIFO_LOWAT 2

		static int
ig4iic_read(ig4iic_softc_t sc, uint8_t buf, uint16_t len,		ig4iic_read(ig4iic_softc_t sc, uint8_t buf, uint16_t len,
bool repeated_start, bool stop)		bool repeated_start, bool stop)
{		{
uint32_t cmd;		uint32_t cmd;
uint16_t i;		int requested = 0;
		int received = 0;
		int burst, target, lowat = 0;
int error;		int error;

if (len == 0)		if (len == 0)
return (0);		return (0);

		while (received < len) {
		burst = sc->cfg.txfifo_depth -
		(reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);
		if (burst <= 0) {
		error = wait_intr(sc, IG4_INTR_TX_EMPTY);
		if (error)
		break;
		burst = sc->cfg.txfifo_depth;
		}
		/* Ensure we have enough free space in RXFIFO */
		burst = MIN(burst, sc->cfg.rxfifo_depth - lowat);
		target = MIN(requested + burst, (int)len);
		while (requested < target) {
cmd = IG4_DATA_COMMAND_RD;		cmd = IG4_DATA_COMMAND_RD;
cmd \|= repeated_start ? IG4_DATA_RESTART : 0;		if (repeated_start && requested == 0)
cmd \|= stop && len == 1 ? IG4_DATA_STOP : 0;		cmd \|= IG4_DATA_RESTART;
		if (stop && requested == len - 1)
/* Issue request for the first byte (could be last as well). */		cmd \|= IG4_DATA_STOP;
reg_write(sc, IG4_REG_DATA_CMD, cmd);		reg_write(sc, IG4_REG_DATA_CMD, cmd);
		requested++;
for (i = 0; i < len; i++) {
/*
* Maintain a pipeline by queueing the allowance for the next
* read before waiting for the current read.
*/
cmd = IG4_DATA_COMMAND_RD;
if (i < len - 1) {
cmd = IG4_DATA_COMMAND_RD;
cmd \|= stop && i == len - 2 ? IG4_DATA_STOP : 0;
reg_write(sc, IG4_REG_DATA_CMD, cmd);
}		}
error = wait_status(sc, IG4_STATUS_RX_NOTEMPTY);		/* Leave some data queued to maintain the hardware pipeline */
		lowat = 0;
		if (requested != len && requested - received > IG4_FIFO_LOWAT)
		lowat = IG4_FIFO_LOWAT;
		/* After TXFLR fills up, clear it by reading available data */
		while (received < requested - lowat) {
		burst = MIN((int)len - received,
		reg_read(sc, IG4_REG_RXFLR) & IG4_FIFOLVL_MASK);
		if (burst > 0) {
		while (burst--)
		buf[received++] = 0xFF &
		reg_read(sc, IG4_REG_DATA_CMD);
		} else {
		error = wait_intr(sc, IG4_INTR_RX_FULL);
if (error)		if (error)
break;		goto out;
buf[i] = data_read(sc);
}		}
		}
(void)reg_read(sc, IG4_REG_TX_ABRT_SOURCE);		}
		out:
return (error);		return (error);
}		}

static int		static int
ig4iic_write(ig4iic_softc_t sc, uint8_t buf, uint16_t len,		ig4iic_write(ig4iic_softc_t sc, uint8_t buf, uint16_t len,
bool repeated_start, bool stop)		bool repeated_start, bool stop)
{		{
uint32_t cmd;		uint32_t cmd;
uint16_t i;		int sent = 0;
		int burst, target;
int error;		int error;
		bool lowat_set = false;

if (len == 0)		if (len == 0)
return (0);		return (0);

cmd = repeated_start ? IG4_DATA_RESTART : 0;		while (sent < len) {
for (i = 0; i < len; i++) {		burst = sc->cfg.txfifo_depth -
error = wait_status(sc, IG4_STATUS_TX_NOTFULL);		(reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);
		target = MIN(sent + burst, (int)len);
		/* Leave some data queued to maintain the hardware pipeline */
		if (!lowat_set && target != len) {
		lowat_set = true;
		reg_write(sc, IG4_REG_TX_TL, IG4_FIFO_LOWAT);
		}
		while(sent < target) {
		cmd = buf[sent];
		if (repeated_start && sent == 0)
		cmd \|= IG4_DATA_RESTART;
		if (stop && sent == len - 1)
		cmd \|= IG4_DATA_STOP;
		reg_write(sc, IG4_REG_DATA_CMD, cmd);
		sent++;
		}
		if (sent < len) {
		error = wait_intr(sc, IG4_INTR_TX_EMPTY);
if (error)		if (error)
break;		break;
cmd \|= buf[i];
cmd \|= stop && i == len - 1 ? IG4_DATA_STOP : 0;
reg_write(sc, IG4_REG_DATA_CMD, cmd);
cmd = 0;
}		}
		}
		if (lowat_set)
		reg_write(sc, IG4_REG_TX_TL, 0);

(void)reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
return (error);		return (error);
}		}

int		int
ig4iic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)		ig4iic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
{		{
ig4iic_softc_t *sc = device_get_softc(dev);		ig4iic_softc_t *sc = device_get_softc(dev);
const char *reason = NULL;		const char *reason = NULL;
uint32_t i;		uint32_t i;
int error;		int error;
int unit;		int unit;
bool rpstart;		bool rpstart;
bool stop;		bool stop;
		bool allocated;

/*		/*
* The hardware interface imposes limits on allowed I2C messages.		* The hardware interface imposes limits on allowed I2C messages.
* It is not possible to explicitly send a start or stop.		* It is not possible to explicitly send a start or stop.
* They are automatically sent (or not sent, depending on the		* They are automatically sent (or not sent, depending on the
* configuration) when a data byte is transferred.		* configuration) when a data byte is transferred.
* For this reason it's impossible to send a message with no data		* For this reason it's impossible to send a message with no data
* at all (like an SMBus quick message).		* at all (like an SMBus quick message).
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines	#endif
}		}
}		}
if (reason != NULL) {		if (reason != NULL) {
if (bootverbose)		if (bootverbose)
device_printf(dev, "%s\n", reason);		device_printf(dev, "%s\n", reason);
return (IIC_ENOTSUPP);		return (IIC_ENOTSUPP);
}		}

		/* Check if device is already allocated with iicbus_request_bus() */
		allocated = sx_xlocked(&sc->call_lock) != 0;
		if (!allocated)
sx_xlock(&sc->call_lock);		sx_xlock(&sc->call_lock);
mtx_lock(&sc->io_lock);

/* Debugging - dump registers. */		/* Debugging - dump registers. */
if (ig4_dump) {		if (ig4_dump) {
unit = device_get_unit(dev);		unit = device_get_unit(dev);
if (ig4_dump & (1 << unit)) {		if (ig4_dump & (1 << unit)) {
ig4_dump &= ~(1 << unit);		ig4_dump &= ~(1 << unit);
ig4iic_dump(sc);		ig4iic_dump(sc);
}		}
}		}

/*		/*
* Clear any previous abort condition that may have been holding		* Clear any previous abort condition that may have been holding
* the txfifo in reset.		* the txfifo in reset.
*/		*/
reg_read(sc, IG4_REG_CLR_TX_ABORT);		reg_read(sc, IG4_REG_CLR_TX_ABORT);

/*
* Clean out any previously received data.
*/
if (sc->rpos != sc->rnext && bootverbose) {
device_printf(sc->dev, "discarding %d bytes of spurious data\n",
sc->rnext - sc->rpos);
}
sc->rpos = 0;
sc->rnext = 0;

rpstart = false;		rpstart = false;
error = 0;		error = 0;
for (i = 0; i < nmsgs; i++) {		for (i = 0; i < nmsgs; i++) {
if ((msgs[i].flags & IIC_M_NOSTART) == 0) {		if ((msgs[i].flags & IIC_M_NOSTART) == 0) {
error = ig4iic_xfer_start(sc, msgs[i].slave);		error = ig4iic_xfer_start(sc, msgs[i].slave, rpstart);
} else {		} else {
if (!sc->slave_valid \|\|		if (!sc->slave_valid \|\|
(msgs[i].slave >> 1) != sc->last_slave) {		(msgs[i].slave >> 1) != sc->last_slave) {
device_printf(dev, "start condition suppressed"		device_printf(dev, "start condition suppressed"
"but slave address is not set up");		"but slave address is not set up");
error = EINVAL;		error = EINVAL;
break;		break;
}		}
rpstart = false;		rpstart = false;
}		}
if (error != 0)		if (error != 0)
break;		break;

stop = (msgs[i].flags & IIC_M_NOSTOP) == 0;		stop = (msgs[i].flags & IIC_M_NOSTOP) == 0;
if (msgs[i].flags & IIC_M_RD)		if (msgs[i].flags & IIC_M_RD)
error = ig4iic_read(sc, msgs[i].buf, msgs[i].len,		error = ig4iic_read(sc, msgs[i].buf, msgs[i].len,
rpstart, stop);		rpstart, stop);
else		else
error = ig4iic_write(sc, msgs[i].buf, msgs[i].len,		error = ig4iic_write(sc, msgs[i].buf, msgs[i].len,
rpstart, stop);		rpstart, stop);
if (error != 0)
		/* Wait for error or stop condition occurred on the I2C bus */
		if (stop && error == 0) {
		error = wait_intr(sc, IG4_INTR_STOP_DET);
		if (error == 0)
		reg_read(sc, IG4_REG_CLR_INTR);
		}

		if (error != 0) {
		/*
		* Send STOP condition if it's not done yet and flush
		* both FIFOs. Do a controller soft reset if transfer
		* abort is failed.
		*/
		if (ig4iic_xfer_is_started(sc) &&
		ig4iic_xfer_abort(sc) != 0) {
		device_printf(sc->dev, "Failed to abort "
		"transfer. Do the controller reset.\n");
		ig4iic_set_config(sc, true);
		} else {
		while (reg_read(sc, IG4_REG_I2C_STA) &
		IG4_STATUS_RX_NOTEMPTY)
		reg_read(sc, IG4_REG_DATA_CMD);
		reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
		reg_read(sc, IG4_REG_CLR_INTR);
		}
break;		break;
		}

rpstart = !stop;		rpstart = !stop;
}		}

mtx_unlock(&sc->io_lock);		if (!allocated)
sx_unlock(&sc->call_lock);		sx_unlock(&sc->call_lock);
return (error);		return (error);
}		}

int		int
ig4iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)		ig4iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
{		{
ig4iic_softc_t *sc = device_get_softc(dev);		ig4iic_softc_t *sc = device_get_softc(dev);
		bool allocated;

		allocated = sx_xlocked(&sc->call_lock) != 0;
		if (!allocated)
sx_xlock(&sc->call_lock);		sx_xlock(&sc->call_lock);
mtx_lock(&sc->io_lock);

/* TODO handle speed configuration? */		/* TODO handle speed configuration? */
if (oldaddr != NULL)		if (oldaddr != NULL)
*oldaddr = sc->last_slave << 1;		*oldaddr = sc->last_slave << 1;
set_slave_addr(sc, addr >> 1);		set_slave_addr(sc, addr >> 1);
if (addr == IIC_UNKNOWN)		if (addr == IIC_UNKNOWN)
sc->slave_valid = false;		sc->slave_valid = false;

mtx_unlock(&sc->io_lock);		if (!allocated)
sx_unlock(&sc->call_lock);		sx_unlock(&sc->call_lock);
return (0);		return (0);
}		}

		int
		ig4iic_callback(device_t dev, int index, caddr_t data)
		{
		ig4iic_softc_t *sc = device_get_softc(dev);
		int error = 0;
		int how;

/*		/*
* Called from ig4iic_pci_attach/detach()		* Unfortunately, iicbus_request_bus() can return error code in both
		* formats, POSIX and IIC. Here we use EAGAIN instead of IIC_EBUSBSY
		* to match other possibly buggy iicbus_callback implementations.
		* As iicbus_poll() returns IIC_EBUSBSY, caller should check returned
		* value for both EAGAIN and IIC_EBUSBSY. Other error codes are POSIX.
*/		*/
		impUnsubmitted Done Inline Actions Meta note: we need to fix this... imp: Meta note: we need to fix this...
		wulfAuthorUnsubmitted Done Inline Actions Recently, r352338 extended IIC error codes with POSIX values. So this note is not relevant to THIS driver anymore, as it returns extended IIC error codes now. wulf: Recently, r352338 extended IIC error codes with POSIX values. So this note is not relevant to…
int		switch (index) {
ig4iic_attach(ig4iic_softc_t *sc)		case IIC_REQUEST_BUS:
		/* force polling if ig4iic is requested with IIC_DONTWAIT */
		how = (int )data;
		if ((how & IIC_WAIT) == 0) {
		if (sx_try_xlock(&sc->call_lock) == 0)
		error = EWOULDBLOCK;
		else
		sc->poll = true;
		} else
		sx_xlock(&sc->call_lock);
		break;

		case IIC_RELEASE_BUS:
		sc->poll = false;
		sx_unlock(&sc->call_lock);
		break;

		default:
		error = EINVAL;
		}

		return (error);
		}

		#ifdef DEV_ACPI
		static int
		ig4iic_acpi_params(ig4iic_softc_t sc, char method,
		uint16_t scl_hcnt, uint16_t scl_lcnt, uint16_t *sda_tx_hold)
{		{
		ACPI_BUFFER buf;
		ACPI_HANDLE handle;
		ACPI_OBJECT obj, elems;
int error;		int error;

		handle = acpi_get_handle(sc->dev);
		if (handle == NULL)
		return (ENXIO);

		buf.Pointer = NULL;
		buf.Length = ACPI_ALLOCATE_BUFFER;

		if (ACPI_FAILURE(AcpiEvaluateObject(handle, method, NULL, &buf)))
		return (ENXIO);

		error = ENXIO;
		obj = (ACPI_OBJECT *)buf.Pointer;
		if (obj->Type == ACPI_TYPE_PACKAGE && obj->Package.Count == 3) {
		elems = obj->Package.Elements;
		*scl_hcnt = elems[0].Integer.Value & IG4_SCL_CLOCK_MASK;
		*scl_lcnt = elems[1].Integer.Value & IG4_SCL_CLOCK_MASK;
		*sda_tx_hold = elems[2].Integer.Value & IG4_SDA_TX_HOLD_MASK;
		error = 0;
		}

		AcpiOsFree(obj);

		return (error);
		}
		#endif /* DEV_ACPI */

		static void
		ig4iic_get_config(ig4iic_softc_t *sc)
		{
		const struct ig4_cfg *cfg;
uint32_t v;		uint32_t v;
		#ifdef DEV_ACPI
		uint16_t sda_tx_hold;
		#endif

mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_DEF);		/* Fetch default hardware config from controller */
sx_init(&sc->call_lock, "IG4 call lock");		sc->cfg.version = reg_read(sc, IG4_REG_COMP_VER);
		sc->cfg.bus_speed = reg_read(sc, IG4_REG_CTL) & IG4_CTL_SPEED_MASK;
		sc->cfg.ss_scl_hcnt =
		reg_read(sc, IG4_REG_SS_SCL_HCNT) & IG4_SCL_CLOCK_MASK;
		sc->cfg.ss_scl_lcnt =
		reg_read(sc, IG4_REG_SS_SCL_LCNT) & IG4_SCL_CLOCK_MASK;
		sc->cfg.fs_scl_hcnt =
		reg_read(sc, IG4_REG_FS_SCL_HCNT) & IG4_SCL_CLOCK_MASK;
		sc->cfg.fs_scl_lcnt =
		reg_read(sc, IG4_REG_FS_SCL_LCNT) & IG4_SCL_CLOCK_MASK;
		sc->cfg.sda_tx_hold =
		reg_read(sc, IG4_REG_SDA_HOLD) & IG4_SDA_TX_HOLD_MASK;

		if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {
		/* REG_COMP_PARAM1 register is not documented in Intel specs */
		v = reg_read(sc, IG4_REG_COMP_PARAM1);
		if (IG4_PARAM1_TXFIFO_DEPTH(v) != 0)
		sc->cfg.txfifo_depth = IG4_PARAM1_TXFIFO_DEPTH(v);
		if (IG4_PARAM1_RXFIFO_DEPTH(v) != 0)
		sc->cfg.rxfifo_depth = IG4_PARAM1_RXFIFO_DEPTH(v);
		} else {
		/*
		* Hardware does not allow FIFO Threshold Levels value to be
		* set larger than the depth of the buffer. If an attempt is
		* made to do that, the actual value set will be the maximum
		* depth of the buffer.
		*/
		v = reg_read(sc, IG4_REG_TX_TL);
		reg_write(sc, IG4_REG_TX_TL, v \| IG4_FIFO_MASK);
		sc->cfg.txfifo_depth =
		(reg_read(sc, IG4_REG_TX_TL) & IG4_FIFO_MASK) + 1;
		reg_write(sc, IG4_REG_TX_TL, v);
		v = reg_read(sc, IG4_REG_RX_TL);
		reg_write(sc, IG4_REG_RX_TL, v \| IG4_FIFO_MASK);
		sc->cfg.rxfifo_depth =
		(reg_read(sc, IG4_REG_RX_TL) & IG4_FIFO_MASK) + 1;
		reg_write(sc, IG4_REG_RX_TL, v);
		}

		/* Override hardware config with precalculated counter values */
		if (ig4_timings < 2 && sc->version < nitems(ig4iic_configs)) {
		cfg = &ig4iic_configs[sc->version];
		if (cfg->bus_speed != 0)
		sc->cfg.bus_speed = cfg->bus_speed;
		if (cfg->ss_scl_hcnt != 0)
		sc->cfg.ss_scl_hcnt = cfg->ss_scl_hcnt;
		if (cfg->ss_scl_lcnt != 0)
		sc->cfg.ss_scl_lcnt = cfg->ss_scl_lcnt;
		if (cfg->fs_scl_hcnt != 0)
		sc->cfg.fs_scl_hcnt = cfg->fs_scl_hcnt;
		if (cfg->fs_scl_lcnt != 0)
		sc->cfg.fs_scl_lcnt = cfg->fs_scl_lcnt;
		if (cfg->sda_tx_hold != 0)
		sc->cfg.sda_tx_hold = cfg->sda_tx_hold;
		if (cfg->txfifo_depth != 0)
		sc->cfg.txfifo_depth = cfg->txfifo_depth;
		if (cfg->rxfifo_depth != 0)
		sc->cfg.rxfifo_depth = cfg->rxfifo_depth;
		} else if (ig4_timings == 2) {
		/*
		* Traditional (Haswell?) timings of original ig4 driver.
		* Program based on a 25000 Hz clock. This is a bit of a
		* hack (obviously). The defaults are 400 and 470 for standard
		* and 60 and 130 for fast. The defaults for standard fail
		* utterly (presumably cause an abort) because the clock time
		* is ~18.8ms by default. This brings it down to ~4ms.
		*/
		sc->cfg.bus_speed = IG4_CTL_SPEED_STD;
		sc->cfg.ss_scl_hcnt = 100;
		sc->cfg.ss_scl_lcnt = 125;
		sc->cfg.fs_scl_hcnt = 100;
		sc->cfg.fs_scl_lcnt = 125;
		/* XXX: SDA_HOLD=28 is valid for Skylake controllers only */
		if (IG4_HAS_ADDREGS(sc->version))
		sc->cfg.sda_tx_hold = 28;
		sc->cfg.txfifo_depth = 16; /* Very conservative value */
		sc->cfg.rxfifo_depth = 16;
		}

		if (sc->cfg.bus_speed != IG4_CTL_SPEED_STD)
		sc->cfg.bus_speed = IG4_CTL_SPEED_FAST;

		#ifdef DEV_ACPI
		/* Evaluate SSCN and FMCN ACPI methods to fetch timings */
		if (ig4_timings == 0 &&
		ig4iic_acpi_params(sc, "SSCN",
		&sc->cfg.ss_scl_hcnt, &sc->cfg.ss_scl_lcnt, &sda_tx_hold) == 0 &&
		sc->cfg.bus_speed == IG4_CTL_SPEED_STD &&
		sda_tx_hold != 0)
		sc->cfg.sda_tx_hold = sda_tx_hold;
		if (ig4_timings == 0 &&
		ig4iic_acpi_params(sc, "FMCN",
		&sc->cfg.fs_scl_hcnt, &sc->cfg.fs_scl_lcnt, &sda_tx_hold) == 0 &&
		sc->cfg.bus_speed == IG4_CTL_SPEED_FAST &&
		sda_tx_hold != 0)
		sc->cfg.sda_tx_hold = sda_tx_hold;
		#endif
		}

		static int
		ig4iic_set_config(ig4iic_softc_t *sc, bool reset)
		{
		uint32_t v;

v = reg_read(sc, IG4_REG_DEVIDLE_CTRL);		v = reg_read(sc, IG4_REG_DEVIDLE_CTRL);
if (sc->version == IG4_SKYLAKE && (v & IG4_RESTORE_REQUIRED) ) {		if (IG4_HAS_ADDREGS(sc->version) && (v & IG4_RESTORE_REQUIRED)) {
reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE \| IG4_RESTORE_REQUIRED);		reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE \| IG4_RESTORE_REQUIRED);
reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0);		reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0);
		pause("i2crst", 1);
		reset = true;
		}

		if ((sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) && reset) {
		reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW);
		reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW);
		} else if (IG4_HAS_ADDREGS(sc->version) && reset) {
reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);		reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL);		reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL);
DELAY(1000);
}		}

if (sc->version == IG4_ATOM)		if (sc->version == IG4_ATOM)
v = reg_read(sc, IG4_REG_COMP_TYPE);		v = reg_read(sc, IG4_REG_COMP_TYPE);

if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {		if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {
v = reg_read(sc, IG4_REG_COMP_PARAM1);		v = reg_read(sc, IG4_REG_COMP_PARAM1);
v = reg_read(sc, IG4_REG_GENERAL);		v = reg_read(sc, IG4_REG_GENERAL);
/*		/*
* The content of IG4_REG_GENERAL is different for each		* The content of IG4_REG_GENERAL is different for each
* controller version.		* controller version.
*/		*/
if (sc->version == IG4_HASWELL &&		if (sc->version == IG4_HASWELL &&
(v & IG4_GENERAL_SWMODE) == 0) {		(v & IG4_GENERAL_SWMODE) == 0) {
v \|= IG4_GENERAL_SWMODE;		v \|= IG4_GENERAL_SWMODE;
reg_write(sc, IG4_REG_GENERAL, v);		reg_write(sc, IG4_REG_GENERAL, v);
v = reg_read(sc, IG4_REG_GENERAL);		v = reg_read(sc, IG4_REG_GENERAL);
}		}
}		}

if (sc->version == IG4_HASWELL) {		if (sc->version == IG4_HASWELL) {
v = reg_read(sc, IG4_REG_SW_LTR_VALUE);		v = reg_read(sc, IG4_REG_SW_LTR_VALUE);
v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);		v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);
} else if (sc->version == IG4_SKYLAKE) {		} else if (IG4_HAS_ADDREGS(sc->version)) {
v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE);		v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE);
v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE);		v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE);
}		}

if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {		if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {
v = reg_read(sc, IG4_REG_COMP_VER);		v = reg_read(sc, IG4_REG_COMP_VER);
if (v < IG4_COMP_MIN_VER) {		if (v < IG4_COMP_MIN_VER)
error = ENXIO;		return(ENXIO);
goto done;
}		}

		if (set_controller(sc, 0)) {
		device_printf(sc->dev, "controller error during attach-1\n");
		return (ENXIO);
}		}
v = reg_read(sc, IG4_REG_SS_SCL_HCNT);
v = reg_read(sc, IG4_REG_SS_SCL_LCNT);
v = reg_read(sc, IG4_REG_FS_SCL_HCNT);
v = reg_read(sc, IG4_REG_FS_SCL_LCNT);
v = reg_read(sc, IG4_REG_SDA_HOLD);

v = reg_read(sc, IG4_REG_SS_SCL_HCNT);		reg_read(sc, IG4_REG_CLR_INTR);
reg_write(sc, IG4_REG_FS_SCL_HCNT, v);		reg_write(sc, IG4_REG_INTR_MASK, 0);
v = reg_read(sc, IG4_REG_SS_SCL_LCNT);		sc->intr_mask = 0;
reg_write(sc, IG4_REG_FS_SCL_LCNT, v);

/*		reg_write(sc, IG4_REG_SS_SCL_HCNT, sc->cfg.ss_scl_hcnt);
* Program based on a 25000 Hz clock. This is a bit of a		reg_write(sc, IG4_REG_SS_SCL_LCNT, sc->cfg.ss_scl_lcnt);
* hack (obviously). The defaults are 400 and 470 for standard		reg_write(sc, IG4_REG_FS_SCL_HCNT, sc->cfg.fs_scl_hcnt);
* and 60 and 130 for fast. The defaults for standard fail		reg_write(sc, IG4_REG_FS_SCL_LCNT, sc->cfg.fs_scl_lcnt);
* utterly (presumably cause an abort) because the clock time		reg_write(sc, IG4_REG_SDA_HOLD, sc->cfg.sda_tx_hold);
* is ~18.8ms by default. This brings it down to ~4ms (for now).
*/
reg_write(sc, IG4_REG_SS_SCL_HCNT, 100);
reg_write(sc, IG4_REG_SS_SCL_LCNT, 125);
reg_write(sc, IG4_REG_FS_SCL_HCNT, 100);
reg_write(sc, IG4_REG_FS_SCL_LCNT, 125);
if (sc->version == IG4_SKYLAKE)
reg_write(sc, IG4_REG_SDA_HOLD, 28);

/*		/*
* Use a threshold of 1 so we get interrupted on each character,		* Use a threshold of 1 so we get interrupted on each character,
* allowing us to use mtx_sleep() in our poll code. Not perfect		* allowing us to use mtx_sleep() in our poll code. Not perfect
* but this is better than using DELAY() for receiving data.		* but this is better than using DELAY() for receiving data.
*		*
* See ig4_var.h for details on interrupt handler synchronization.		* See ig4_var.h for details on interrupt handler synchronization.
*/		*/
reg_write(sc, IG4_REG_RX_TL, 1);		reg_write(sc, IG4_REG_RX_TL, 0);
		reg_write(sc, IG4_REG_TX_TL, 0);

reg_write(sc, IG4_REG_CTL,		reg_write(sc, IG4_REG_CTL,
IG4_CTL_MASTER \|		IG4_CTL_MASTER \|
IG4_CTL_SLAVE_DISABLE \|		IG4_CTL_SLAVE_DISABLE \|
IG4_CTL_RESTARTEN \|		IG4_CTL_RESTARTEN \|
IG4_CTL_SPEED_STD);		(sc->cfg.bus_speed & IG4_CTL_SPEED_MASK));

		/* Force setting of the target address on the next transfer */
		sc->slave_valid = 0;

		return (0);
		}

		/*
		* Called from ig4iic_pci_attach/detach()
		*/
		int
		ig4iic_attach(ig4iic_softc_t *sc)
		{
		int error;

		mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_DEF);
		sx_init(&sc->call_lock, "IG4 call lock");

		ig4iic_get_config(sc);

		error = ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version));
		if (error)
		goto done;

sc->iicbus = device_add_child(sc->dev, "iicbus", -1);		sc->iicbus = device_add_child(sc->dev, "iicbus", -1);
if (sc->iicbus == NULL) {		if (sc->iicbus == NULL) {
device_printf(sc->dev, "iicbus driver not found\n");		device_printf(sc->dev, "iicbus driver not found\n");
error = ENXIO;		error = ENXIO;
goto done;		goto done;
}		}

#if 0		if (set_controller(sc, IG4_I2C_ENABLE)) {
/*
* Don't do this, it blows up the PCI config
*/
if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {
reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW);
reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW);
} else if (sc->version = IG4_SKYLAKE) {
reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL);
}
#endif

mtx_lock(&sc->io_lock);
if (set_controller(sc, 0))
device_printf(sc->dev, "controller error during attach-1\n");
if (set_controller(sc, IG4_I2C_ENABLE))
device_printf(sc->dev, "controller error during attach-2\n");		device_printf(sc->dev, "controller error during attach-2\n");
mtx_unlock(&sc->io_lock);		error = ENXIO;
		goto done;
		}
		if (set_controller(sc, 0)) {
		device_printf(sc->dev, "controller error during attach-3\n");
		error = ENXIO;
		goto done;
		}
error = bus_setup_intr(sc->dev, sc->intr_res, INTR_TYPE_MISC \| INTR_MPSAFE,		error = bus_setup_intr(sc->dev, sc->intr_res, INTR_TYPE_MISC \| INTR_MPSAFE,
NULL, ig4iic_intr, sc, &sc->intr_handle);		NULL, ig4iic_intr, sc, &sc->intr_handle);
if (error) {		if (error) {
device_printf(sc->dev,		device_printf(sc->dev,
"Unable to setup irq: error %d\n", error);		"Unable to setup irq: error %d\n", error);
}		}

sc->enum_hook.ich_func = ig4iic_start;
sc->enum_hook.ich_arg = sc->dev;

/*
* We have to wait until interrupts are enabled. I2C read and write
* only works if the interrupts are available.
*/
if (config_intrhook_establish(&sc->enum_hook) != 0)
error = ENOMEM;
else
error = 0;

done:
return (error);
}

void
ig4iic_start(void *xdev)
{
int error;
ig4iic_softc_t *sc;
device_t dev = (device_t)xdev;

sc = device_get_softc(dev);

config_intrhook_disestablish(&sc->enum_hook);

error = bus_generic_attach(sc->dev);		error = bus_generic_attach(sc->dev);
if (error) {		if (error) {
device_printf(sc->dev,		device_printf(sc->dev,
"failed to attach child: error %d\n", error);		"failed to attach child: error %d\n", error);
}		}

		done:
		return (error);
}		}

int		int
ig4iic_detach(ig4iic_softc_t *sc)		ig4iic_detach(ig4iic_softc_t *sc)
{		{
int error;		int error;

if (device_is_attached(sc->dev)) {		if (device_is_attached(sc->dev)) {
error = bus_generic_detach(sc->dev);		error = bus_generic_detach(sc->dev);
if (error)		if (error)
return (error);		return (error);
}		}
if (sc->iicbus)		if (sc->iicbus)
device_delete_child(sc->dev, sc->iicbus);		device_delete_child(sc->dev, sc->iicbus);
if (sc->intr_handle)		if (sc->intr_handle)
bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle);		bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle);

sx_xlock(&sc->call_lock);		sx_xlock(&sc->call_lock);
mtx_lock(&sc->io_lock);

sc->iicbus = NULL;		sc->iicbus = NULL;
sc->intr_handle = NULL;		sc->intr_handle = NULL;
reg_write(sc, IG4_REG_INTR_MASK, 0);		reg_write(sc, IG4_REG_INTR_MASK, 0);
set_controller(sc, 0);		set_controller(sc, 0);

mtx_unlock(&sc->io_lock);
sx_xunlock(&sc->call_lock);		sx_xunlock(&sc->call_lock);

mtx_destroy(&sc->io_lock);		mtx_destroy(&sc->io_lock);
sx_destroy(&sc->call_lock);		sx_destroy(&sc->call_lock);

return (0);		return (0);
}		}

		int
		ig4iic_suspend(ig4iic_softc_t *sc)
		{
		int error;

		/* suspend all children */
		error = bus_generic_suspend(sc->dev);

		sx_xlock(&sc->call_lock);
		set_controller(sc, 0);
		if (IG4_HAS_ADDREGS(sc->version)) {
/*		/*
		* Place the device in the idle state, just to be safe
		*/
		reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE);
		/*
		* Controller can become unfunctional if I2C lines are pulled
		impUnsubmitted Done Inline Actions Unfunctional is not a word. Dysfunctional is what you want. imp: Unfunctional is not a word. Dysfunctional is what you want.
		wulfAuthorUnsubmitted Done Inline Actions Fixed. Thanks. wulf: Fixed. Thanks.
		* down when suspend procedure turns off power to I2C device.
		* Place device in the reset state to avoid this.
		*/
		reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
		}
		sx_xunlock(&sc->call_lock);

		return (error);
		}

		int ig4iic_resume(ig4iic_softc_t *sc)
		{
		int error;

		sx_xlock(&sc->call_lock);
		if (ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version)))
		device_printf(sc->dev, "controller error during resume\n");
		sx_xunlock(&sc->call_lock);

		error = bus_generic_resume(sc->dev);

		return (error);
		}

		/*
* Interrupt Operation, see ig4_var.h for locking semantics.		* Interrupt Operation, see ig4_var.h for locking semantics.
*/		*/
static void		static void
ig4iic_intr(void *cookie)		ig4iic_intr(void *cookie)
{		{
ig4iic_softc_t *sc = cookie;		ig4iic_softc_t *sc = cookie;
uint32_t status;		uint32_t status;

mtx_lock(&sc->io_lock);		mtx_lock(&sc->io_lock);
/* reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET);*/		if (sc->intr_mask != 0) {
reg_read(sc, IG4_REG_CLR_INTR);		status = reg_read(sc, IG4_REG_INTR_STAT);
status = reg_read(sc, IG4_REG_I2C_STA);		set_intr_mask(sc, 0);
while (status & IG4_STATUS_RX_NOTEMPTY) {		sc->error = intrstat2iic(sc, status);
sc->rbuf[sc->rnext & IG4_RBUFMASK] =
(uint8_t)reg_read(sc, IG4_REG_DATA_CMD);
++sc->rnext;
status = reg_read(sc, IG4_REG_I2C_STA);
}

/*
* Workaround to trigger pending interrupt if IG4_REG_INTR_STAT
* is changed after clearing it
*/
if (sc->access_intr_mask != 0) {
status = reg_read(sc, IG4_REG_INTR_MASK);
if (status != 0) {
reg_write(sc, IG4_REG_INTR_MASK, 0);
reg_write(sc, IG4_REG_INTR_MASK, status);
}
}

wakeup(sc);		wakeup(sc);
		} else
		reg_write(sc, IG4_REG_INTR_MASK, 0);
mtx_unlock(&sc->io_lock);		mtx_unlock(&sc->io_lock);
}		}

#define REGDUMP(sc, reg) \		#define REGDUMP(sc, reg) \
device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg))		device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg))

static void		static void
ig4iic_dump(ig4iic_softc_t *sc)		ig4iic_dump(ig4iic_softc_t *sc)
Show All 17 Lines	ig4iic_dump(ig4iic_softc_t *sc)
REGDUMP(sc, IG4_REG_SDA_HOLD);		REGDUMP(sc, IG4_REG_SDA_HOLD);
REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE);		REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE);
REGDUMP(sc, IG4_REG_SLV_DATA_NACK);		REGDUMP(sc, IG4_REG_SLV_DATA_NACK);
REGDUMP(sc, IG4_REG_DMA_CTRL);		REGDUMP(sc, IG4_REG_DMA_CTRL);
REGDUMP(sc, IG4_REG_DMA_TDLR);		REGDUMP(sc, IG4_REG_DMA_TDLR);
REGDUMP(sc, IG4_REG_DMA_RDLR);		REGDUMP(sc, IG4_REG_DMA_RDLR);
REGDUMP(sc, IG4_REG_SDA_SETUP);		REGDUMP(sc, IG4_REG_SDA_SETUP);
REGDUMP(sc, IG4_REG_ENABLE_STATUS);		REGDUMP(sc, IG4_REG_ENABLE_STATUS);
if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {
REGDUMP(sc, IG4_REG_COMP_PARAM1);		REGDUMP(sc, IG4_REG_COMP_PARAM1);
REGDUMP(sc, IG4_REG_COMP_VER);		REGDUMP(sc, IG4_REG_COMP_VER);
}
if (sc->version == IG4_ATOM) {		if (sc->version == IG4_ATOM) {
REGDUMP(sc, IG4_REG_COMP_TYPE);		REGDUMP(sc, IG4_REG_COMP_TYPE);
REGDUMP(sc, IG4_REG_CLK_PARMS);		REGDUMP(sc, IG4_REG_CLK_PARMS);
}		}
if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {		if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {
REGDUMP(sc, IG4_REG_RESETS_HSW);		REGDUMP(sc, IG4_REG_RESETS_HSW);
REGDUMP(sc, IG4_REG_GENERAL);		REGDUMP(sc, IG4_REG_GENERAL);
} else if (sc->version == IG4_SKYLAKE) {		} else if (sc->version == IG4_SKYLAKE) {
REGDUMP(sc, IG4_REG_RESETS_SKL);		REGDUMP(sc, IG4_REG_RESETS_SKL);
}		}
if (sc->version == IG4_HASWELL) {		if (sc->version == IG4_HASWELL) {
REGDUMP(sc, IG4_REG_SW_LTR_VALUE);		REGDUMP(sc, IG4_REG_SW_LTR_VALUE);
REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE);		REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE);
} else if (sc->version == IG4_SKYLAKE) {		} else if (IG4_HAS_ADDREGS(sc->version)) {
REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE);		REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE);
REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE);		REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE);
}		}
}		}
#undef REGDUMP		#undef REGDUMP

DRIVER_MODULE(iicbus, ig4iic_acpi, iicbus_driver, iicbus_devclass, NULL, NULL);		devclass_t ig4iic_devclass;
DRIVER_MODULE(iicbus, ig4iic_pci, iicbus_driver, iicbus_devclass, NULL, NULL);
		DRIVER_MODULE(iicbus, ig4iic, iicbus_driver, iicbus_devclass, NULL, NULL);
		MODULE_DEPEND(ig4iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);
		MODULE_VERSION(ig4iic, 1);