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arm64/arm64/locore.S
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/* Link the DMAP tables */ | /* Link the DMAP tables */ | ||||
ldr x8, =DMAP_MIN_ADDRESS | ldr x8, =DMAP_MIN_ADDRESS | ||||
adr x9, pagetable_dmap; | adr x9, pagetable_dmap; | ||||
mov x10, #DMAP_TABLES | mov x10, #DMAP_TABLES | ||||
bl link_l0_pagetable | bl link_l0_pagetable | ||||
/* | /* | ||||
* Build the TTBR0 maps. | * Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_nG. | ||||
* They are only needed early on, so the VA = PA map is uncached. | |||||
*/ | */ | ||||
add x27, x24, #PAGE_SIZE | add x27, x24, #PAGE_SIZE | ||||
mov x6, x27 /* The initial page table */ | mov x6, x27 /* The initial page table */ | ||||
#if defined(SOCDEV_PA) && defined(SOCDEV_VA) | #if defined(SOCDEV_PA) && defined(SOCDEV_VA) | ||||
/* Create a table for the UART */ | /* Create a table for the UART */ | ||||
mov x7, #DEVICE_MEM | mov x7, #(ATTR_nG | ATTR_IDX(DEVICE_MEM)) | ||||
mov x8, #(SOCDEV_VA) /* VA start */ | mov x8, #(SOCDEV_VA) /* VA start */ | ||||
mov x9, #(SOCDEV_PA) /* PA start */ | mov x9, #(SOCDEV_PA) /* PA start */ | ||||
mov x10, #1 | mov x10, #1 | ||||
bl build_l1_block_pagetable | bl build_l1_block_pagetable | ||||
#endif | #endif | ||||
/* Create the VA = PA map */ | /* Create the VA = PA map */ | ||||
mov x7, #NORMAL_UNCACHED /* Uncached as it's only needed early on */ | mov x7, #(ATTR_nG | ATTR_IDX(NORMAL_UNCACHED)) | ||||
mov x9, x27 | mov x9, x27 | ||||
mov x8, x9 /* VA start (== PA start) */ | mov x8, x9 /* VA start (== PA start) */ | ||||
mov x10, #1 | mov x10, #1 | ||||
bl build_l1_block_pagetable | bl build_l1_block_pagetable | ||||
/* Move to the l0 table */ | /* Move to the l0 table */ | ||||
add x27, x27, #PAGE_SIZE | add x27, x27, #PAGE_SIZE | ||||
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/* Store the entry */ | /* Store the entry */ | ||||
str x13, [x6, x11, lsl #3] | str x13, [x6, x11, lsl #3] | ||||
ret | ret | ||||
/* | /* | ||||
* Builds count 1 GiB page table entry | * Builds count 1 GiB page table entry | ||||
* x6 = L1 table | * x6 = L1 table | ||||
* x7 = Type (0 = Device, 1 = Normal) | * x7 = Variable lower block attributes | ||||
* x8 = VA start | * x8 = VA start | ||||
* x9 = PA start (trashed) | * x9 = PA start (trashed) | ||||
* x10 = Entry count | * x10 = Entry count | ||||
* x11, x12 and x13 are trashed | * x11, x12 and x13 are trashed | ||||
*/ | */ | ||||
build_l1_block_pagetable: | build_l1_block_pagetable: | ||||
/* | /* | ||||
* Build the L1 table entry. | * Build the L1 table entry. | ||||
*/ | */ | ||||
/* Find the table index */ | /* Find the table index */ | ||||
lsr x11, x8, #L1_SHIFT | lsr x11, x8, #L1_SHIFT | ||||
and x11, x11, #Ln_ADDR_MASK | and x11, x11, #Ln_ADDR_MASK | ||||
/* Build the L1 block entry */ | /* Build the L1 block entry */ | ||||
lsl x12, x7, #2 | orr x12, x7, #L1_BLOCK | ||||
orr x12, x12, #L1_BLOCK | |||||
orr x12, x12, #(ATTR_AF) | orr x12, x12, #(ATTR_AF) | ||||
#ifdef SMP | #ifdef SMP | ||||
orr x12, x12, ATTR_SH(ATTR_SH_IS) | orr x12, x12, ATTR_SH(ATTR_SH_IS) | ||||
#endif | #endif | ||||
/* Only use the output address bits */ | /* Only use the output address bits */ | ||||
lsr x9, x9, #L1_SHIFT | lsr x9, x9, #L1_SHIFT | ||||
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/* Invalidate the TLB */ | /* Invalidate the TLB */ | ||||
tlbi vmalle1is | tlbi vmalle1is | ||||
ldr x2, mair | ldr x2, mair | ||||
msr mair_el1, x2 | msr mair_el1, x2 | ||||
/* | /* | ||||
* Setup TCR according to PARange bits from ID_AA64MMFR0_EL1. | * Setup TCR according to the PARange and ASIDBits fields | ||||
* from ID_AA64MMFR0_EL1. More precisely, set TCR_EL1.AS | |||||
* to 1 only if the ASIDBits field equals 0b0010. | |||||
*/ | */ | ||||
ldr x2, tcr | ldr x2, tcr | ||||
mrs x3, id_aa64mmfr0_el1 | mrs x3, id_aa64mmfr0_el1 | ||||
bfi x2, x3, #32, #3 | bfi x2, x3, #32, #3 | ||||
and x3, x3, #0xF0 | |||||
cmp x3, #0x20 | |||||
cset x3, eq | |||||
bfi x2, x3, #36, #1 | |||||
msr tcr_el1, x2 | msr tcr_el1, x2 | ||||
/* Setup SCTLR */ | /* Setup SCTLR */ | ||||
ldr x2, sctlr_set | ldr x2, sctlr_set | ||||
ldr x3, sctlr_clear | ldr x3, sctlr_clear | ||||
mrs x1, sctlr_el1 | mrs x1, sctlr_el1 | ||||
bic x1, x1, x3 /* Clear the required bits */ | bic x1, x1, x3 /* Clear the required bits */ | ||||
orr x1, x1, x2 /* Set the required bits */ | orr x1, x1, x2 /* Set the required bits */ | ||||
msr sctlr_el1, x1 | msr sctlr_el1, x1 | ||||
isb | isb | ||||
ret | ret | ||||
.align 3 | .align 3 | ||||
mair: | mair: | ||||
.quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, 0) | \ | .quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, 0) | \ | ||||
MAIR_ATTR(MAIR_NORMAL_NC, 1) | \ | MAIR_ATTR(MAIR_NORMAL_NC, 1) | \ | ||||
MAIR_ATTR(MAIR_NORMAL_WB, 2) | \ | MAIR_ATTR(MAIR_NORMAL_WB, 2) | \ | ||||
MAIR_ATTR(MAIR_NORMAL_WT, 3) | MAIR_ATTR(MAIR_NORMAL_WT, 3) | ||||
tcr: | tcr: | ||||
.quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | TCR_TG1_4K | \ | .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG1_4K | \ | ||||
TCR_CACHE_ATTRS | TCR_SMP_ATTRS) | TCR_CACHE_ATTRS | TCR_SMP_ATTRS) | ||||
sctlr_set: | sctlr_set: | ||||
/* Bits to set */ | /* Bits to set */ | ||||
.quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \ | .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \ | ||||
SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ | SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ | ||||
SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \ | SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \ | ||||
SCTLR_M | SCTLR_CP15BEN) | SCTLR_M | SCTLR_CP15BEN) | ||||
sctlr_clear: | sctlr_clear: | ||||
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