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sys/dev/mlx4/mlx4_core/mlx4_eq.c
| Show First 20 Lines • Show All 1,245 Lines • ▼ Show 20 Lines | snprintf(priv->eq_table.irq_names + | ||||
| MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE, | MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE, | ||||
| MLX4_IRQNAME_SIZE, | MLX4_IRQNAME_SIZE, | ||||
| "mlx4-async@pci:%s", | "mlx4-async@pci:%s", | ||||
| pci_name(dev->persist->pdev)); | pci_name(dev->persist->pdev)); | ||||
| eq_name = priv->eq_table.irq_names + | eq_name = priv->eq_table.irq_names + | ||||
| MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE; | MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE; | ||||
| err = request_irq(priv->eq_table.eq[MLX4_EQ_ASYNC].irq, | err = request_irq(priv->eq_table.eq[MLX4_EQ_ASYNC].irq, | ||||
| mlx4_msi_x_interrupt, 0, eq_name, | mlx4_msi_x_interrupt, 0, NULL, | ||||
| priv->eq_table.eq + MLX4_EQ_ASYNC); | priv->eq_table.eq + MLX4_EQ_ASYNC); | ||||
| if (err) | if (err) | ||||
| goto err_out_unmap; | goto err_out_unmap; | ||||
| priv->eq_table.eq[MLX4_EQ_ASYNC].have_irq = 1; | priv->eq_table.eq[MLX4_EQ_ASYNC].have_irq = 1; | ||||
| } else { | } else { | ||||
| snprintf(priv->eq_table.irq_names, | snprintf(priv->eq_table.irq_names, | ||||
| MLX4_IRQNAME_SIZE, | MLX4_IRQNAME_SIZE, | ||||
| DRV_NAME "@pci:%s", | DRV_NAME "@pci:%s", | ||||
| pci_name(dev->persist->pdev)); | pci_name(dev->persist->pdev)); | ||||
| err = request_irq(dev->persist->pdev->irq, mlx4_interrupt, | err = request_irq(dev->persist->pdev->irq, mlx4_interrupt, | ||||
| IRQF_SHARED, priv->eq_table.irq_names, dev); | IRQF_SHARED, NULL, dev); | ||||
| if (err) | if (err) | ||||
| goto err_out_unmap; | goto err_out_unmap; | ||||
| priv->eq_table.have_irq = 1; | priv->eq_table.have_irq = 1; | ||||
| } | } | ||||
| err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, | err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, | ||||
| priv->eq_table.eq[MLX4_EQ_ASYNC].eqn); | priv->eq_table.eq[MLX4_EQ_ASYNC].eqn); | ||||
| ▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Lines | if (!test_bit(*prequested_vector, priv->msix_ctl.pool_bm) && | ||||
| set_bit(*prequested_vector, priv->msix_ctl.pool_bm); | set_bit(*prequested_vector, priv->msix_ctl.pool_bm); | ||||
| snprintf(priv->eq_table.irq_names + | snprintf(priv->eq_table.irq_names + | ||||
| *prequested_vector * MLX4_IRQNAME_SIZE, | *prequested_vector * MLX4_IRQNAME_SIZE, | ||||
| MLX4_IRQNAME_SIZE, "mlx4-%d@%s", | MLX4_IRQNAME_SIZE, "mlx4-%d@%s", | ||||
| *prequested_vector, dev_name(&dev->persist->pdev->dev)); | *prequested_vector, dev_name(&dev->persist->pdev->dev)); | ||||
| err = request_irq(priv->eq_table.eq[*prequested_vector].irq, | err = request_irq(priv->eq_table.eq[*prequested_vector].irq, | ||||
| mlx4_msi_x_interrupt, 0, | mlx4_msi_x_interrupt, 0, | ||||
| &priv->eq_table.irq_names[*prequested_vector << 5], | NULL, | ||||
| priv->eq_table.eq + *prequested_vector); | priv->eq_table.eq + *prequested_vector); | ||||
| if (err) { | if (err) { | ||||
| clear_bit(*prequested_vector, priv->msix_ctl.pool_bm); | clear_bit(*prequested_vector, priv->msix_ctl.pool_bm); | ||||
| *prequested_vector = -1; | *prequested_vector = -1; | ||||
| } else { | } else { | ||||
| mlx4_set_eq_affinity_hint(priv, *prequested_vector); | mlx4_set_eq_affinity_hint(priv, *prequested_vector); | ||||
| eq_set_ci(&priv->eq_table.eq[*prequested_vector], 1); | eq_set_ci(&priv->eq_table.eq[*prequested_vector], 1); | ||||
| ▲ Show 20 Lines • Show All 73 Lines • Show Last 20 Lines | |||||