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Show First 20 Lines • Show All 460 Lines • ▼ Show 20 Lines	int mlx5_create_map_eq(struct mlx5_core_dev dev, struct mlx5_eq eq, u8 vecidx,

eq->eqn = MLX5_GET(create_eq_out, out, eq_number);		eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
eq->irqn = vecidx;		eq->irqn = vecidx;
eq->dev = dev;		eq->dev = dev;
eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET;		eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET;
snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",		snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
name, pci_name(dev->pdev));		name, pci_name(dev->pdev));
err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0,		err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0,
priv->irq_info[vecidx].name, eq);		NULL, eq);
if (err)		if (err)
goto err_eq;		goto err_eq;
#ifdef RSS		#ifdef RSS
if (vecidx >= MLX5_EQ_VEC_COMP_BASE) {		if (vecidx >= MLX5_EQ_VEC_COMP_BASE) {
u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE;		u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE;
err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector,		err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector,
rss_getcpu(bucket % rss_getnumbuckets()));		rss_getcpu(bucket % rss_getnumbuckets()));
if (err)		if (err)
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