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head/sys/amd64/amd64/pmap.c
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| Show First 20 Lines • Show All 1,533 Lines • ▼ Show 20 Lines | create_pagetables(vm_paddr_t *firstaddr) | ||||
| for (i = 0; i < ndm1g; i++) { | for (i = 0; i < ndm1g; i++) { | ||||
| pdp_p[i] = (vm_paddr_t)i << PDPSHIFT; | pdp_p[i] = (vm_paddr_t)i << PDPSHIFT; | ||||
| /* Preset PG_M and PG_A because demotion expects it. */ | /* Preset PG_M and PG_A because demotion expects it. */ | ||||
| pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g | | pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g | | ||||
| X86_PG_M | X86_PG_A | pg_nx; | X86_PG_M | X86_PG_A | pg_nx; | ||||
| } | } | ||||
| for (j = 0; i < ndmpdp; i++, j++) { | for (j = 0; i < ndmpdp; i++, j++) { | ||||
| pdp_p[i] = DMPDphys + ptoa(j); | pdp_p[i] = DMPDphys + ptoa(j); | ||||
| pdp_p[i] |= X86_PG_RW | X86_PG_V; | pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx; | ||||
| } | } | ||||
| /* | /* | ||||
| * Instead of using a 1G page for the memory containing the kernel, | * Instead of using a 1G page for the memory containing the kernel, | ||||
| * use 2M pages with appropriate permissions. (If using 1G pages, | * use 2M pages with read-only and no-execute permissions. (If using 1G | ||||
| * this will partially overwrite the PDPEs above.) | * pages, this will partially overwrite the PDPEs above.) | ||||
| */ | */ | ||||
| if (ndm1g) { | if (ndm1g) { | ||||
| pd_p = (pd_entry_t *)DMPDkernphys; | pd_p = (pd_entry_t *)DMPDkernphys; | ||||
| for (i = 0; i < (NPDEPG * nkdmpde); i++) | for (i = 0; i < (NPDEPG * nkdmpde); i++) | ||||
| pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g | | pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g | | ||||
| X86_PG_M | X86_PG_A | pg_nx | | X86_PG_M | X86_PG_A | pg_nx | | ||||
| bootaddr_rwx(i << PDRSHIFT); | bootaddr_rwx(i << PDRSHIFT); | ||||
| for (i = 0; i < nkdmpde; i++) | for (i = 0; i < nkdmpde; i++) | ||||
| pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW | | pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW | | ||||
| X86_PG_V; | X86_PG_V | pg_nx; | ||||
| } | } | ||||
| /* And recursively map PML4 to itself in order to get PTmap */ | /* And recursively map PML4 to itself in order to get PTmap */ | ||||
| p4_p = (pml4_entry_t *)KPML4phys; | p4_p = (pml4_entry_t *)KPML4phys; | ||||
| p4_p[PML4PML4I] = KPML4phys; | p4_p[PML4PML4I] = KPML4phys; | ||||
| p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx; | p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx; | ||||
| /* Connect the Direct Map slot(s) up to the PML4. */ | /* Connect the Direct Map slot(s) up to the PML4. */ | ||||
| for (i = 0; i < ndmpdpphys; i++) { | for (i = 0; i < ndmpdpphys; i++) { | ||||
| p4_p[DMPML4I + i] = DMPDPphys + ptoa(i); | p4_p[DMPML4I + i] = DMPDPphys + ptoa(i); | ||||
| p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V; | p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx; | ||||
| } | } | ||||
| /* Connect the KVA slots up to the PML4 */ | /* Connect the KVA slots up to the PML4 */ | ||||
| for (i = 0; i < NKPML4E; i++) { | for (i = 0; i < NKPML4E; i++) { | ||||
| p4_p[KPML4BASE + i] = KPDPphys + ptoa(i); | p4_p[KPML4BASE + i] = KPDPphys + ptoa(i); | ||||
| p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V; | p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V; | ||||
| } | } | ||||
| } | } | ||||
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