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head/sys/arm64/arm64/gic_v3_reg.h
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*/ | */ | ||||
#define LPI_CONF_PRIO_MASK (0xFC) | #define LPI_CONF_PRIO_MASK (0xFC) | ||||
#define LPI_CONF_GROUP1 (1 << 1) | #define LPI_CONF_GROUP1 (1 << 1) | ||||
#define LPI_CONF_ENABLE (1 << 0) | #define LPI_CONF_ENABLE (1 << 0) | ||||
/* | /* | ||||
* CPU interface | * CPU interface | ||||
*/ | */ | ||||
#define GICI_SGI_TLIST_MASK (0xffffUL) | |||||
#define GICI_SGI_AFF1_SHIFT (16UL) | |||||
#define GICI_SGI_AFF2_SHIFT (32UL) | |||||
#define GICI_SGI_AFF3_SHIFT (48UL) | |||||
#define GICI_SGI_IPI_MASK (0xfUL) | |||||
#define GICI_SGI_IPI_SHIFT (24UL) | |||||
/* | /* | ||||
* Registers list (ICC_xyz_EL1): | * Registers list (ICC_xyz_EL1): | ||||
* | * | ||||
* PMR - Priority Mask Register | * PMR - Priority Mask Register | ||||
* * interrupts of priority higher than specified | * * interrupts of priority higher than specified | ||||
* in this mask will be signalled to the CPU. | * in this mask will be signalled to the CPU. | ||||
* (0xff - lowest possible prio., 0x00 - highest prio.) | * (0xff - lowest possible prio., 0x00 - highest prio.) | ||||
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