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	#define MDIO_AN_INT 0x8002			#define MDIO_AN_INT 0x8002
	#endif			#endif

	#ifndef MDIO_CTRL1_SPEED1G			#ifndef MDIO_CTRL1_SPEED1G
	#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)			#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
	#endif			#endif

	/* MDIO mask values */			/* MDIO mask values */
				#define XGBE_AN_CL73_INT_CMPLT BIT(0)
				#define XGBE_AN_CL73_INC_LINK BIT(1)
				#define XGBE_AN_CL73_PG_RCV BIT(2)
				#define XGBE_AN_CL73_INT_MASK 0x07

	#define XGBE_XNP_MCF_NULL_MESSAGE 0x001			#define XGBE_XNP_MCF_NULL_MESSAGE 0x001
	#define XGBE_XNP_ACK_PROCESSED BIT(12)			#define XGBE_XNP_ACK_PROCESSED BIT(12)
	#define XGBE_XNP_MP_FORMATTED BIT(13)			#define XGBE_XNP_MP_FORMATTED BIT(13)
	#define XGBE_XNP_NP_EXCHANGE BIT(15)			#define XGBE_XNP_NP_EXCHANGE BIT(15)

	#define XGBE_KR_TRAINING_START BIT(0)			#define XGBE_KR_TRAINING_START BIT(0)
	#define XGBE_KR_TRAINING_ENABLE BIT(1)			#define XGBE_KR_TRAINING_ENABLE BIT(1)

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