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Show First 20 Lines • Show All 163 Lines • ▼ Show 20 Lines	if (pidx >= map->size \|\| BIT_ISSET(map->size, pidx, map->err))
return (VM_PAGER_FAIL);		return (VM_PAGER_FAIL);

page = PHYS_TO_VM_PAGE(map->phys_base_addr + offset);		page = PHYS_TO_VM_PAGE(map->phys_base_addr + offset);
if (page == NULL)		if (page == NULL)
return (VM_PAGER_FAIL);		return (VM_PAGER_FAIL);

KASSERT((page->flags & PG_FICTITIOUS) != 0,		KASSERT((page->flags & PG_FICTITIOUS) != 0,
("not fictitious %p", page));		("not fictitious %p", page));
KASSERT(page->wire_count == 1, ("wire_count not 1 %p", page));		KASSERT(vm_page_wired(page), ("page %p not wired", page));
KASSERT(vm_page_busied(page) == 0, ("page %p is busy", page));		KASSERT(!vm_page_busied(page), ("page %p is busy", page));

if (*mres != NULL) {		if (*mres != NULL) {
oldm = *mres;		oldm = *mres;
vm_page_lock(oldm);
vm_page_free(oldm);		vm_page_free(oldm);
vm_page_unlock(oldm);
*mres = NULL;		*mres = NULL;
}		}

vm_page_insert(page, object, pidx);		vm_page_insert(page, object, pidx);
page->valid = VM_PAGE_BITS_ALL;		page->valid = VM_PAGE_BITS_ALL;
vm_page_xbusy(page);		vm_page_xbusy(page);
*mres = page;		*mres = page;
return (VM_PAGER_OK);		return (VM_PAGER_OK);
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