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sys/amd64/include/pmap.h

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* used to implement the direct map. It must be a power of two, * used to implement the direct map. It must be a power of two,
* and should generally exceed NKPML4E. The maximum possible * and should generally exceed NKPML4E. The maximum possible
* value is 64; using 128 will make the direct map intrude into * value is 64; using 128 will make the direct map intrude into
* the recursive page table map. * the recursive page table map.
*/ */
#define NDMPML4E 8 #define NDMPML4E 8
/* /*
* NPAPML4E is the maximum number of PML4 entries that will be
* used to implement the page array. This should be roughly 3% of
* NPDPML4E owing to 3% overhead for struct vm_page.
*/
#define NPAPML4E 1
/*
* These values control the layout of virtual memory. The starting address * These values control the layout of virtual memory. The starting address
* of the direct map, which is controlled by DMPML4I, must be a multiple of * of the direct map, which is controlled by DMPML4I, must be a multiple of
* its size. (See the PHYS_TO_DMAP() and DMAP_TO_PHYS() macros.) * its size. (See the PHYS_TO_DMAP() and DMAP_TO_PHYS() macros.)
* *
* Note: KPML4I is the index of the (single) level 4 page that maps * Note: KPML4I is the index of the (single) level 4 page that maps
* the KVA that holds KERNBASE, while KPML4BASE is the index of the * the KVA that holds KERNBASE, while KPML4BASE is the index of the
* first level 4 page that maps VM_MIN_KERNEL_ADDRESS. If NKPML4E * first level 4 page that maps VM_MIN_KERNEL_ADDRESS. If NKPML4E
* is 1, these are the same, otherwise KPML4BASE < KPML4I and extra * is 1, these are the same, otherwise KPML4BASE < KPML4I and extra
* level 4 PDEs are needed to map from VM_MIN_KERNEL_ADDRESS up to * level 4 PDEs are needed to map from VM_MIN_KERNEL_ADDRESS up to
* KERNBASE. * KERNBASE.
* *
* (KPML4I combines with KPDPI to choose where KERNBASE starts. * (KPML4I combines with KPDPI to choose where KERNBASE starts.
* Or, in other words, KPML4I provides bits 39..47 of KERNBASE, * Or, in other words, KPML4I provides bits 39..47 of KERNBASE,
* and KPDPI provides bits 30..38.) * and KPDPI provides bits 30..38.)
*/ */
#define PML4PML4I (NPML4EPG/2) /* Index of recursive pml4 mapping */ #define PML4PML4I (NPML4EPG/2) /* Index of recursive pml4 mapping */
#define KPML4BASE (NPML4EPG-NKPML4E) /* KVM at highest addresses */ #define KPML4BASE (NPML4EPG-NKPML4E) /* KVM at highest addresses */
#define DMPML4I rounddown(KPML4BASE-NDMPML4E, NDMPML4E) /* Below KVM */ #define PAPML4I (KPML4BASE-1-NPAPML4E) /* Below KVM */
#define DMPML4I rounddown(PAPML4I-NDMPML4E, NDMPML4E) /* Below pages */
kibUnsubmitted
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So the page array pml4 entry is just below DMAP, am I right ? And the large map max size is reduced by 512G ?

You should update the map in amd64/include/vmparam.h under the comment 'Virtual addresses of things'.

kib: So the page array pml4 entry is just below DMAP, am I right ? And the large map max size is…
jeffAuthorUnsubmitted
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After this comment I decided to move it down and make sure it had a guard region on either side.

There was a gap between KPML4BASE and DMPML4I that was just big enough. If direct map must be naturally aligned then when it doubles there will still be space even if kva doubles.

I verified the vmparam.h values with gdb.

jeff: After this comment I decided to move it down and make sure it had a guard region on either side.
#define KPML4I (NPML4EPG-1) #define KPML4I (NPML4EPG-1)
#define KPDPI (NPDPEPG-2) /* kernbase at -2GB */ #define KPDPI (NPDPEPG-2) /* kernbase at -2GB */
/* Large map: index of the first and max last pml4 entry */ /* Large map: index of the first and max last pml4 entry */
#define LMSPML4I (PML4PML4I + 1) #define LMSPML4I (PML4PML4I + 1)
#define LMEPML4I (DMPML4I - 1) #define LMEPML4I (DMPML4I - 1)
kibUnsubmitted
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This is strange, this line should be shown as changed. Do you have some issue with the patch generation ?

kib: This is strange, this line should be shown as changed. Do you have some issue with the patch…
/* /*
* XXX doesn't really belong here I guess... * XXX doesn't really belong here I guess...
*/ */
#define ISA_HOLE_START 0xa0000 #define ISA_HOLE_START 0xa0000
#define ISA_HOLE_LENGTH (0x100000-ISA_HOLE_START) #define ISA_HOLE_LENGTH (0x100000-ISA_HOLE_START)
#define PMAP_PCID_NONE 0xffffffff #define PMAP_PCID_NONE 0xffffffff
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void pmap_pti_pcid_invlpg(uint64_t ucr3, uint64_t kcr3, vm_offset_t va); void pmap_pti_pcid_invlpg(uint64_t ucr3, uint64_t kcr3, vm_offset_t va);
void pmap_pti_pcid_invlrng(uint64_t ucr3, uint64_t kcr3, vm_offset_t sva, void pmap_pti_pcid_invlrng(uint64_t ucr3, uint64_t kcr3, vm_offset_t sva,
vm_offset_t eva); vm_offset_t eva);
int pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva); int pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
int pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
u_int keyidx, int flags); u_int keyidx, int flags);
void pmap_thread_init_invl_gen(struct thread *td); void pmap_thread_init_invl_gen(struct thread *td);
int pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap); int pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap);
void pmap_page_array_startup(long count);
#endif /* _KERNEL */ #endif /* _KERNEL */
/* Return various clipped indexes for a given VA */ /* Return various clipped indexes for a given VA */
static __inline vm_pindex_t static __inline vm_pindex_t
pmap_pte_index(vm_offset_t va) pmap_pte_index(vm_offset_t va)
{ {
return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1)); return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
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