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head/sys/dev/ixgbe/if_ix.c
Show First 20 Lines • Show All 419 Lines • ▼ Show 20 Lines | ixgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, | ||||
for (i = 0, que = adapter->tx_queues; i < ntxqsets; i++, que++) { | for (i = 0, que = adapter->tx_queues; i < ntxqsets; i++, que++) { | ||||
struct tx_ring *txr = &que->txr; | struct tx_ring *txr = &que->txr; | ||||
/* In case SR-IOV is enabled, align the index properly */ | /* In case SR-IOV is enabled, align the index properly */ | ||||
txr->me = ixgbe_vf_que_index(adapter->iov_mode, adapter->pool, | txr->me = ixgbe_vf_que_index(adapter->iov_mode, adapter->pool, | ||||
i); | i); | ||||
txr->adapter = que->adapter = adapter; | txr->adapter = que->adapter = adapter; | ||||
adapter->active_queues |= (u64)1 << txr->me; | |||||
/* Allocate report status array */ | /* Allocate report status array */ | ||||
txr->tx_rsq = (qidx_t *)malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_IXGBE, M_NOWAIT | M_ZERO); | txr->tx_rsq = (qidx_t *)malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_IXGBE, M_NOWAIT | M_ZERO); | ||||
if (txr->tx_rsq == NULL) { | if (txr->tx_rsq == NULL) { | ||||
error = ENOMEM; | error = ENOMEM; | ||||
goto fail; | goto fail; | ||||
} | } | ||||
for (j = 0; j < scctx->isc_ntxd[0]; j++) | for (j = 0; j < scctx->isc_ntxd[0]; j++) | ||||
▲ Show 20 Lines • Show All 354 Lines • ▼ Show 20 Lines | for (i = 0, que = adapter->tx_queues; i < adapter->num_tx_queues; | ||||
IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), | ||||
scctx->isc_ntxd[0] * sizeof(union ixgbe_adv_tx_desc)); | scctx->isc_ntxd[0] * sizeof(union ixgbe_adv_tx_desc)); | ||||
/* Setup the HW Tx Head and Tail descriptor pointers */ | /* Setup the HW Tx Head and Tail descriptor pointers */ | ||||
IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); | IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); | ||||
IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); | IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); | ||||
/* Cache the tail address */ | /* Cache the tail address */ | ||||
txr->tail = IXGBE_TDT(txr->me); | |||||
txr->tx_rs_cidx = txr->tx_rs_pidx; | txr->tx_rs_cidx = txr->tx_rs_pidx; | ||||
txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; | txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; | ||||
for (int k = 0; k < scctx->isc_ntxd[0]; k++) | for (int k = 0; k < scctx->isc_ntxd[0]; k++) | ||||
txr->tx_rsq[k] = QIDX_INVALID; | txr->tx_rsq[k] = QIDX_INVALID; | ||||
/* Disable Head Writeback */ | /* Disable Head Writeback */ | ||||
/* | /* | ||||
* Note: for X550 series devices, these registers are actually | * Note: for X550 series devices, these registers are actually | ||||
▲ Show 20 Lines • Show All 1,190 Lines • ▼ Show 20 Lines | for (int i = 0; i < adapter->num_rx_queues; i++, vector++, rx_que++) { | ||||
if (error) { | if (error) { | ||||
device_printf(iflib_get_dev(ctx), | device_printf(iflib_get_dev(ctx), | ||||
"Failed to allocate que int %d err: %d", i, error); | "Failed to allocate que int %d err: %d", i, error); | ||||
adapter->num_rx_queues = i + 1; | adapter->num_rx_queues = i + 1; | ||||
goto fail; | goto fail; | ||||
} | } | ||||
rx_que->msix = vector; | rx_que->msix = vector; | ||||
adapter->active_queues |= (u64)(1 << rx_que->msix); | |||||
if (adapter->feat_en & IXGBE_FEATURE_RSS) { | if (adapter->feat_en & IXGBE_FEATURE_RSS) { | ||||
/* | /* | ||||
* The queue ID is used as the RSS layer bucket ID. | * The queue ID is used as the RSS layer bucket ID. | ||||
* We look up the queue ID -> RSS CPU ID and select | * We look up the queue ID -> RSS CPU ID and select | ||||
* that. | * that. | ||||
*/ | */ | ||||
cpu_id = rss_getcpu(i % rss_getnumbuckets()); | cpu_id = rss_getcpu(i % rss_getnumbuckets()); | ||||
} else { | } else { | ||||
▲ Show 20 Lines • Show All 1,668 Lines • ▼ Show 20 Lines | |||||
* ixgbe_if_rx_queue_intr_enable | * ixgbe_if_rx_queue_intr_enable | ||||
************************************************************************/ | ************************************************************************/ | ||||
static int | static int | ||||
ixgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) | ixgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) | ||||
{ | { | ||||
struct adapter *adapter = iflib_get_softc(ctx); | struct adapter *adapter = iflib_get_softc(ctx); | ||||
struct ix_rx_queue *que = &adapter->rx_queues[rxqid]; | struct ix_rx_queue *que = &adapter->rx_queues[rxqid]; | ||||
ixgbe_enable_queue(adapter, que->rxr.me); | ixgbe_enable_queue(adapter, que->msix); | ||||
return (0); | return (0); | ||||
} /* ixgbe_if_rx_queue_intr_enable */ | } /* ixgbe_if_rx_queue_intr_enable */ | ||||
/************************************************************************ | /************************************************************************ | ||||
* ixgbe_enable_queue | * ixgbe_enable_queue | ||||
************************************************************************/ | ************************************************************************/ | ||||
static void | static void | ||||
ixgbe_enable_queue(struct adapter *adapter, u32 vector) | ixgbe_enable_queue(struct adapter *adapter, u32 vector) | ||||
{ | { | ||||
struct ixgbe_hw *hw = &adapter->hw; | struct ixgbe_hw *hw = &adapter->hw; | ||||
u64 queue = (u64)(1 << vector); | u64 queue = 1ULL << vector; | ||||
u32 mask; | u32 mask; | ||||
if (hw->mac.type == ixgbe_mac_82598EB) { | if (hw->mac.type == ixgbe_mac_82598EB) { | ||||
mask = (IXGBE_EIMS_RTX_QUEUE & queue); | mask = (IXGBE_EIMS_RTX_QUEUE & queue); | ||||
IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); | IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); | ||||
} else { | } else { | ||||
mask = (queue & 0xFFFFFFFF); | mask = (queue & 0xFFFFFFFF); | ||||
if (mask) | if (mask) | ||||
IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); | ||||
mask = (queue >> 32); | mask = (queue >> 32); | ||||
if (mask) | if (mask) | ||||
IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); | ||||
} | } | ||||
} /* ixgbe_enable_queue */ | } /* ixgbe_enable_queue */ | ||||
/************************************************************************ | /************************************************************************ | ||||
* ixgbe_disable_queue | * ixgbe_disable_queue | ||||
************************************************************************/ | ************************************************************************/ | ||||
static void | static void | ||||
ixgbe_disable_queue(struct adapter *adapter, u32 vector) | ixgbe_disable_queue(struct adapter *adapter, u32 vector) | ||||
{ | { | ||||
struct ixgbe_hw *hw = &adapter->hw; | struct ixgbe_hw *hw = &adapter->hw; | ||||
u64 queue = (u64)(1 << vector); | u64 queue = 1ULL << vector; | ||||
u32 mask; | u32 mask; | ||||
if (hw->mac.type == ixgbe_mac_82598EB) { | if (hw->mac.type == ixgbe_mac_82598EB) { | ||||
mask = (IXGBE_EIMS_RTX_QUEUE & queue); | mask = (IXGBE_EIMS_RTX_QUEUE & queue); | ||||
IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); | IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); | ||||
} else { | } else { | ||||
mask = (queue & 0xFFFFFFFF); | mask = (queue & 0xFFFFFFFF); | ||||
if (mask) | if (mask) | ||||
▲ Show 20 Lines • Show All 819 Lines • Show Last 20 Lines |