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head/usr.sbin/bhyve/pci_emul.c
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#define PCIECAP_VERSION 0x2 | #define PCIECAP_VERSION 0x2 | ||||
int | int | ||||
pci_emul_add_pciecap(struct pci_devinst *pi, int type) | pci_emul_add_pciecap(struct pci_devinst *pi, int type) | ||||
{ | { | ||||
int err; | int err; | ||||
struct pciecap pciecap; | struct pciecap pciecap; | ||||
if (type != PCIEM_TYPE_ROOT_PORT) | |||||
return (-1); | |||||
bzero(&pciecap, sizeof(pciecap)); | bzero(&pciecap, sizeof(pciecap)); | ||||
/* | |||||
* Use the integrated endpoint type for endpoints on a root complex bus. | |||||
* | |||||
* NB: bhyve currently only supports a single PCI bus that is the root | |||||
* complex bus, so all endpoints are integrated. | |||||
*/ | |||||
if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0)) | |||||
type = PCIEM_TYPE_ROOT_INT_EP; | |||||
pciecap.capid = PCIY_EXPRESS; | pciecap.capid = PCIY_EXPRESS; | ||||
pciecap.pcie_capabilities = PCIECAP_VERSION | PCIEM_TYPE_ROOT_PORT; | pciecap.pcie_capabilities = PCIECAP_VERSION | type; | ||||
if (type != PCIEM_TYPE_ROOT_INT_EP) { | |||||
pciecap.link_capabilities = 0x411; /* gen1, x1 */ | pciecap.link_capabilities = 0x411; /* gen1, x1 */ | ||||
pciecap.link_status = 0x11; /* gen1, x1 */ | pciecap.link_status = 0x11; /* gen1, x1 */ | ||||
} | |||||
err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); | err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); | ||||
return (err); | return (err); | ||||
} | } | ||||
/* | /* | ||||
* This function assumes that 'coff' is in the capabilities region of the | * This function assumes that 'coff' is in the capabilities region of the | ||||
* config space. | * config space. | ||||
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