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sys/dev/ixl/i40e_osdep.c
/****************************************************************************** | /****************************************************************************** | ||||
Copyright (c) 2013-2017, Intel Corporation | Copyright (c) 2013-2019, Intel Corporation | ||||
All rights reserved. | All rights reserved. | ||||
Redistribution and use in source and binary forms, with or without | Redistribution and use in source and binary forms, with or without | ||||
modification, are permitted provided that the following conditions are met: | modification, are permitted provided that the following conditions are met: | ||||
1. Redistributions of source code must retain the above copyright notice, | 1. Redistributions of source code must retain the above copyright notice, | ||||
this list of conditions and the following disclaimer. | this list of conditions and the following disclaimer. | ||||
2. Redistributions in binary form must reproduce the above copyright | 2. Redistributions in binary form must reproduce the above copyright | ||||
notice, this list of conditions and the following disclaimer in the | notice, this list of conditions and the following disclaimer in the | ||||
Show All 14 Lines | /****************************************************************************** | ||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | ||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ||||
POSSIBILITY OF SUCH DAMAGE. | POSSIBILITY OF SUCH DAMAGE. | ||||
******************************************************************************/ | ******************************************************************************/ | ||||
/*$FreeBSD$*/ | /*$FreeBSD$*/ | ||||
#include <sys/limits.h> | #include <sys/limits.h> | ||||
#include <sys/time.h> | |||||
#include "ixl.h" | #include "ixl.h" | ||||
/******************************************************************** | /******************************************************************** | ||||
* Manage DMA'able memory. | * Manage DMA'able memory. | ||||
*******************************************************************/ | *******************************************************************/ | ||||
static void | static void | ||||
i40e_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nseg, int error) | i40e_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nseg, int error) | ||||
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void | void | ||||
i40e_destroy_spinlock(struct i40e_spinlock *lock) | i40e_destroy_spinlock(struct i40e_spinlock *lock) | ||||
{ | { | ||||
if (mtx_initialized(&lock->mutex)) | if (mtx_initialized(&lock->mutex)) | ||||
mtx_destroy(&lock->mutex); | mtx_destroy(&lock->mutex); | ||||
} | } | ||||
#ifndef MSEC_2_TICKS | |||||
#define MSEC_2_TICKS(m) max(1, (uint32_t)((hz == 1000) ? \ | |||||
(m) : ((uint64_t)(m) * (uint64_t)hz)/(uint64_t)1000)) | |||||
#endif | |||||
void | void | ||||
i40e_msec_pause(int msecs) | i40e_msec_pause(int msecs) | ||||
{ | { | ||||
int ticks_to_pause = (msecs * hz) / 1000; | pause("i40e_msec_pause", MSEC_2_TICKS(msecs)); | ||||
int start_ticks = ticks; | |||||
if (cold || SCHEDULER_STOPPED()) { | |||||
i40e_msec_delay(msecs); | |||||
return; | |||||
} | |||||
while (1) { | |||||
kern_yield(PRI_USER); | |||||
int yielded_ticks = ticks - start_ticks; | |||||
if (yielded_ticks > ticks_to_pause) | |||||
break; | |||||
else if (yielded_ticks < 0 | |||||
&& (yielded_ticks + INT_MAX + 1 > ticks_to_pause)) { | |||||
break; | |||||
} | |||||
} | |||||
} | } | ||||
/* | /* | ||||
* Helper function for debug statement printing | * Helper function for debug statement printing | ||||
*/ | */ | ||||
void | void | ||||
i40e_debug_shared(struct i40e_hw *hw, enum i40e_debug_mask mask, char *fmt, ...) | i40e_debug_shared(struct i40e_hw *hw, enum i40e_debug_mask mask, char *fmt, ...) | ||||
{ | { | ||||
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