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Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines	if (cpu_vendor_intel) {
switch (num) {		switch (num) {
case MSR_HWCR:		case MSR_HWCR:
/*		/*
* Ignore writes to hardware configuration MSR.		* Ignore writes to hardware configuration MSR.
*/		*/
return (0);		return (0);

case MSR_NB_CFG1:		case MSR_NB_CFG1:
		case MSR_LS_CFG:
case MSR_IC_CFG:		case MSR_IC_CFG:
return (0); /* Ignore writes */		return (0); /* Ignore writes */

case MSR_PERFEVSEL0:		case MSR_PERFEVSEL0:
case MSR_PERFEVSEL1:		case MSR_PERFEVSEL1:
case MSR_PERFEVSEL2:		case MSR_PERFEVSEL2:
case MSR_PERFEVSEL3:		case MSR_PERFEVSEL3:
/* Ignore writes to the PerfEvtSel MSRs */		/* Ignore writes to the PerfEvtSel MSRs */
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines	case MSR_HWCR:
* Bios and Kernel Developer's Guides for AMD Families		* Bios and Kernel Developer's Guides for AMD Families
* 12H, 14H, 15H and 16H.		* 12H, 14H, 15H and 16H.
*/		*/
val = 0x01000010; / Reset value */		val = 0x01000010; / Reset value */
val \|= 1 << 9; / MONITOR/MWAIT disable */		val \|= 1 << 9; / MONITOR/MWAIT disable */
break;		break;

case MSR_NB_CFG1:		case MSR_NB_CFG1:
		case MSR_LS_CFG:
case MSR_IC_CFG:		case MSR_IC_CFG:
/*		/*
* The reset value is processor family dependent so		* The reset value is processor family dependent so
* just return 0.		* just return 0.
*/		*/
*val = 0;		*val = 0;
break;		break;

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