Differential D19842 Diff 58060 head/sys/arm64/arm64/gic_v3_var.h

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head/sys/arm64/arm64/gic_v3_var.h

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	#include <arm/arm/gic_common.h>			#include <arm/arm/gic_common.h>

	#define GIC_V3_DEVSTR "ARM Generic Interrupt Controller v3.0"			#define GIC_V3_DEVSTR "ARM Generic Interrupt Controller v3.0"

	DECLARE_CLASS(gic_v3_driver);			DECLARE_CLASS(gic_v3_driver);

	struct gic_v3_irqsrc;			struct gic_v3_irqsrc;

	struct redist_lpis {			struct redist_pcpu {
	vm_offset_t conf_base;			struct resource res;
	vm_offset_t pend_base[MAXCPU];			vm_offset_t pend_base;
	uint64_t flags;
	};			};

	struct gic_redists {			struct gic_redists {
	/*			/*
	* Re-Distributor region description.			* Re-Distributor region description.
	* We will have few of those depending			* We will have few of those depending
	* on the #redistributor-regions property in FDT.			* on the #redistributor-regions property in FDT.
	*/			*/
	struct resource ** regions;			struct resource ** regions;
	/* Number of Re-Distributor regions */			/* Number of Re-Distributor regions */
	u_int nregions;			u_int nregions;
	/* Per-CPU Re-Distributor handler */			/* Per-CPU Re-Distributor data */
	struct resource * pcpu[MAXCPU];			struct redist_pcpu *pcpu[MAXCPU];
	/* LPIs data */
	struct redist_lpis lpis;
	};			};

	struct gic_v3_softc {			struct gic_v3_softc {
	device_t dev;			device_t dev;
	struct resource ** gic_res;			struct resource ** gic_res;
	struct mtx gic_mtx;			struct mtx gic_mtx;
	/* Distributor */			/* Distributor */
	struct resource * gic_dist;			struct resource * gic_dist;
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	#define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc)			#define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc)

	MALLOC_DECLARE(M_GIC_V3);			MALLOC_DECLARE(M_GIC_V3);

	/* ivars */			/* ivars */
	#define GICV3_IVAR_NIRQS 1000			#define GICV3_IVAR_NIRQS 1000
	#define GICV3_IVAR_REDIST_VADDR 1001			#define GICV3_IVAR_REDIST_VADDR 1001
				#define GICV3_IVAR_REDIST 1002

	__BUS_ACCESSOR(gicv3, nirqs, GICV3, NIRQS, u_int);			__BUS_ACCESSOR(gicv3, nirqs, GICV3, NIRQS, u_int);
	__BUS_ACCESSOR(gicv3, redist_vaddr, GICV3, REDIST_VADDR, void *);			__BUS_ACCESSOR(gicv3, redist_vaddr, GICV3, REDIST_VADDR, void *);
				__BUS_ACCESSOR(gicv3, redist, GICV3, REDIST, void *);

	/* Device methods */			/* Device methods */
	int gic_v3_attach(device_t dev);			int gic_v3_attach(device_t dev);
	int gic_v3_detach(device_t dev);			int gic_v3_detach(device_t dev);
	int arm_gic_v3_intr(void *);			int arm_gic_v3_intr(void *);

	uint32_t gic_r_read_4(device_t, bus_size_t);			uint32_t gic_r_read_4(device_t, bus_size_t);
	uint64_t gic_r_read_8(device_t, bus_size_t);			uint64_t gic_r_read_8(device_t, bus_size_t);
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	})			})

	/* GIC Re-Distributor accessors (per-CPU) */			/* GIC Re-Distributor accessors (per-CPU) */
	#define gic_r_read(sc, len, reg) \			#define gic_r_read(sc, len, reg) \
	({ \			({ \
	u_int cpu = PCPU_GET(cpuid); \			u_int cpu = PCPU_GET(cpuid); \
	\			\
	bus_read_##len( \			bus_read_##len( \
	sc->gic_redists.pcpu[cpu], \			&sc->gic_redists.pcpu[cpu]->res, \
	reg); \			reg); \
	})			})

	#define gic_r_write(sc, len, reg, val) \			#define gic_r_write(sc, len, reg, val) \
	({ \			({ \
	u_int cpu = PCPU_GET(cpuid); \			u_int cpu = PCPU_GET(cpuid); \
	\			\
	bus_write_##len( \			bus_write_##len( \
	sc->gic_redists.pcpu[cpu], \			&sc->gic_redists.pcpu[cpu]->res, \
	reg, val); \			reg, val); \
	})			})

	#endif /* _GIC_V3_VAR_H_ */			#endif /* _GIC_V3_VAR_H_ */