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head/sys/amd64/amd64/initcpu.c
| Show First 20 Lines • Show All 118 Lines • ▼ Show 20 Lines | init_amd(void) | ||||
| /* | /* | ||||
| * Work around Erratum 793: Specific Combination of Writes to Write | * Work around Erratum 793: Specific Combination of Writes to Write | ||||
| * Combined Memory Types and Locked Instructions May Cause Core Hang. | * Combined Memory Types and Locked Instructions May Cause Core Hang. | ||||
| * See Revision Guide for AMD Family 16h Models 00h-0Fh Processors, | * See Revision Guide for AMD Family 16h Models 00h-0Fh Processors, | ||||
| * revision 3.04 or later, publication 51810. | * revision 3.04 or later, publication 51810. | ||||
| */ | */ | ||||
| if (CPUID_TO_FAMILY(cpu_id) == 0x16 && CPUID_TO_MODEL(cpu_id) <= 0xf) { | if (CPUID_TO_FAMILY(cpu_id) == 0x16 && CPUID_TO_MODEL(cpu_id) <= 0xf) { | ||||
| if ((cpu_feature2 & CPUID2_HV) == 0) { | if ((cpu_feature2 & CPUID2_HV) == 0) { | ||||
| msr = rdmsr(0xc0011020); | msr = rdmsr(MSR_LS_CFG); | ||||
| msr |= (uint64_t)1 << 15; | msr |= (uint64_t)1 << 15; | ||||
| wrmsr(0xc0011020, msr); | wrmsr(MSR_LS_CFG, msr); | ||||
| } | } | ||||
| } | } | ||||
| /* Ryzen erratas. */ | /* Ryzen erratas. */ | ||||
| if (CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1 && | if (CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1 && | ||||
| (cpu_feature2 & CPUID2_HV) == 0) { | (cpu_feature2 & CPUID2_HV) == 0) { | ||||
| /* 1021 */ | /* 1021 */ | ||||
| msr = rdmsr(0xc0011029); | msr = rdmsr(0xc0011029); | ||||
| msr |= 0x2000; | msr |= 0x2000; | ||||
| wrmsr(0xc0011029, msr); | wrmsr(0xc0011029, msr); | ||||
| /* 1033 */ | /* 1033 */ | ||||
| msr = rdmsr(0xc0011020); | msr = rdmsr(MSR_LS_CFG); | ||||
| msr |= 0x10; | msr |= 0x10; | ||||
| wrmsr(0xc0011020, msr); | wrmsr(MSR_LS_CFG, msr); | ||||
| /* 1049 */ | /* 1049 */ | ||||
| msr = rdmsr(0xc0011028); | msr = rdmsr(0xc0011028); | ||||
| msr |= 0x10; | msr |= 0x10; | ||||
| wrmsr(0xc0011028, msr); | wrmsr(0xc0011028, msr); | ||||
| /* 1095 */ | /* 1095 */ | ||||
| msr = rdmsr(0xc0011020); | msr = rdmsr(MSR_LS_CFG); | ||||
| msr |= 0x200000000000000; | msr |= 0x200000000000000; | ||||
| wrmsr(0xc0011020, msr); | wrmsr(MSR_LS_CFG, msr); | ||||
| } | } | ||||
| /* | /* | ||||
| * Work around a problem on Ryzen that is triggered by executing | * Work around a problem on Ryzen that is triggered by executing | ||||
| * code near the top of user memory, in our case the signal | * code near the top of user memory, in our case the signal | ||||
| * trampoline code in the shared page on amd64. | * trampoline code in the shared page on amd64. | ||||
| * | * | ||||
| * This function is executed once for the BSP before tunables take | * This function is executed once for the BSP before tunables take | ||||
| ▲ Show 20 Lines • Show All 143 Lines • Show Last 20 Lines | |||||