Changeset View
Changeset View
Standalone View
Standalone View
emulators/xen-kernel/files/xsa297-4.12-4.patch
- This file was added.
| Property | Old Value | New Value |
|---|---|---|
| fbsd:nokeywords | null | yes \ No newline at end of property |
| svn:eol-style | null | native \ No newline at end of property |
| svn:mime-type | null | text/plain \ No newline at end of property |
| From: Andrew Cooper <andrew.cooper3@citrix.com> | |||||
| Subject: x86/spec-ctrl: Misc non-functional cleanup | |||||
| * Identify BTI in the spec_ctrl_{enter,exit}_idle() comments, as other | |||||
| mitigations will shortly appear. | |||||
| * Use alternative_input() and cover the lack of memory cobber with a further | |||||
| barrier. | |||||
| Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> | |||||
| Reviewed-by: Jan Beulich <jbeulich@suse.com> | |||||
| diff --git a/xen/include/asm-x86/spec_ctrl.h b/xen/include/asm-x86/spec_ctrl.h | |||||
| index 779da2b..20ee112 100644 | |||||
| --- a/xen/include/asm-x86/spec_ctrl.h | |||||
| +++ b/xen/include/asm-x86/spec_ctrl.h | |||||
| @@ -68,6 +68,8 @@ static always_inline void spec_ctrl_enter_idle(struct cpu_info *info) | |||||
| uint32_t val = 0; | |||||
| /* | |||||
| + * Branch Target Injection: | |||||
| + * | |||||
| * Latch the new shadow value, then enable shadowing, then update the MSR. | |||||
| * There are no SMP issues here; only local processor ordering concerns. | |||||
| */ | |||||
| @@ -75,8 +77,9 @@ static always_inline void spec_ctrl_enter_idle(struct cpu_info *info) | |||||
| barrier(); | |||||
| info->spec_ctrl_flags |= SCF_use_shadow; | |||||
| barrier(); | |||||
| - asm volatile ( ALTERNATIVE("", "wrmsr", X86_FEATURE_SC_MSR_IDLE) | |||||
| - :: "a" (val), "c" (MSR_SPEC_CTRL), "d" (0) : "memory" ); | |||||
| + alternative_input("", "wrmsr", X86_FEATURE_SC_MSR_IDLE, | |||||
| + "a" (val), "c" (MSR_SPEC_CTRL), "d" (0)); | |||||
| + barrier(); | |||||
| } | |||||
| /* WARNING! `ret`, `call *`, `jmp *` not safe before this call. */ | |||||
| @@ -85,13 +88,16 @@ static always_inline void spec_ctrl_exit_idle(struct cpu_info *info) | |||||
| uint32_t val = info->xen_spec_ctrl; | |||||
| /* | |||||
| + * Branch Target Injection: | |||||
| + * | |||||
| * Disable shadowing before updating the MSR. There are no SMP issues | |||||
| * here; only local processor ordering concerns. | |||||
| */ | |||||
| info->spec_ctrl_flags &= ~SCF_use_shadow; | |||||
| barrier(); | |||||
| - asm volatile ( ALTERNATIVE("", "wrmsr", X86_FEATURE_SC_MSR_IDLE) | |||||
| - :: "a" (val), "c" (MSR_SPEC_CTRL), "d" (0) : "memory" ); | |||||
| + alternative_input("", "wrmsr", X86_FEATURE_SC_MSR_IDLE, | |||||
| + "a" (val), "c" (MSR_SPEC_CTRL), "d" (0)); | |||||
| + barrier(); | |||||
| } | |||||
| #endif /* __ASSEMBLY__ */ | |||||