Differential D19833 Diff 56019 head/sys/x86/x86/legacy.c

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head/sys/x86/x86/legacy.c

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	#include <sys/cpu.h>			#include <sys/cpu.h>
	#include <sys/kernel.h>			#include <sys/kernel.h>
	#include <sys/malloc.h>			#include <sys/malloc.h>
	#include <sys/module.h>			#include <sys/module.h>
	#include <machine/bus.h>			#include <machine/bus.h>
	#include <sys/pcpu.h>			#include <sys/pcpu.h>
	#include <sys/rman.h>			#include <sys/rman.h>
	#include <sys/smp.h>			#include <sys/smp.h>
				#include <dev/pci/pcireg.h>

	#include <machine/clock.h>			#include <machine/clock.h>
				#include <machine/pci_cfgreg.h>
	#include <machine/resource.h>			#include <machine/resource.h>
	#include <x86/legacyvar.h>			#include <x86/legacyvar.h>

	static MALLOC_DEFINE(M_LEGACYDEV, "legacydrv", "legacy system device");			static MALLOC_DEFINE(M_LEGACYDEV, "legacydrv", "legacy system device");
	struct legacy_device {			struct legacy_device {
	int lg_pcibus;			int lg_pcibus;
	int lg_pcislot;			int lg_pcislot;
	int lg_pcifunc;			int lg_pcifunc;
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	legacy_probe(device_t dev)			legacy_probe(device_t dev)
	{			{

	device_set_desc(dev, "legacy system");			device_set_desc(dev, "legacy system");
	device_quiet(dev);			device_quiet(dev);
	return (0);			return (0);
	}			}

				/*
				* Grope around in the PCI config space to see if this is a chipset
				* that is capable of doing memory-mapped config cycles. This also
				* implies that it can do PCIe extended config cycles.
				*/
				static void
				legacy_pci_cfgregopen(device_t dev)
				{
				uint64_t pciebar;
				u_int16_t did, vid;

				if (cfgmech == CFGMECH_NONE \|\| cfgmech == CFGMECH_PCIE)
				return;

				/* Check for supported chipsets */
				vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
				did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
				switch (vid) {
				case 0x8086:
				switch (did) {
				case 0x3590:
				case 0x3592:
				/* Intel 7520 or 7320 */
				pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
				pcie_cfgregopen(pciebar, 0, 255);
				break;
				case 0x2580:
				case 0x2584:
				case 0x2590:
				/* Intel 915, 925, or 915GM */
				pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
				pcie_cfgregopen(pciebar, 0, 255);
				break;
				}
				}

				if (bootverbose && cfgmech == CFGMECH_PCIE)
				device_printf(dev, "Enabled ECAM PCIe accesses\n");
				}

	static int			static int
	legacy_attach(device_t dev)			legacy_attach(device_t dev)
	{			{
	device_t child;			device_t child;

				legacy_pci_cfgregopen(dev);

	/*			/*
	* Let our child drivers identify any child devices that they			* Let our child drivers identify any child devices that they
	* can find. Once that is done attach any devices that we			* can find. Once that is done attach any devices that we
	* found.			* found.
	*/			*/
	bus_generic_probe(dev);			bus_generic_probe(dev);
	bus_generic_attach(dev);			bus_generic_attach(dev);
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