Changeset View
Changeset View
Standalone View
Standalone View
usr.sbin/bhyve/uart_emul.c
| /*- | /*- | ||||
| * SPDX-License-Identifier: BSD-2-Clause-FreeBSD | * SPDX-License-Identifier: BSD-2-Clause-FreeBSD | ||||
| * | * | ||||
| * Copyright (c) 2012 NetApp, Inc. | * Copyright (c) 2012 NetApp, Inc. | ||||
| * Copyright (c) 2013 Neel Natu <neel@freebsd.org> | * Copyright (c) 2013 Neel Natu <neel@freebsd.org> | ||||
| * All rights reserved. | * All rights reserved. | ||||
| * Copyright (c) 2018 Joyent, Inc. | |||||
| * | * | ||||
| * Redistribution and use in source and binary forms, with or without | * Redistribution and use in source and binary forms, with or without | ||||
| * modification, are permitted provided that the following conditions | * modification, are permitted provided that the following conditions | ||||
| * are met: | * are met: | ||||
| * 1. Redistributions of source code must retain the above copyright | * 1. Redistributions of source code must retain the above copyright | ||||
| * notice, this list of conditions and the following disclaimer. | * notice, this list of conditions and the following disclaimer. | ||||
| * 2. Redistributions in binary form must reproduce the above copyright | * 2. Redistributions in binary form must reproduce the above copyright | ||||
| * notice, this list of conditions and the following disclaimer in the | * notice, this list of conditions and the following disclaimer in the | ||||
| ▲ Show 20 Lines • Show All 411 Lines • ▼ Show 20 Lines | if (sc->mcr & MCR_LOOPBACK) { | ||||
| if (rxfifo_putchar(sc, value) != 0) | if (rxfifo_putchar(sc, value) != 0) | ||||
| sc->lsr |= LSR_OE; | sc->lsr |= LSR_OE; | ||||
| } else if (sc->tty.opened) { | } else if (sc->tty.opened) { | ||||
| ttywrite(&sc->tty, value); | ttywrite(&sc->tty, value); | ||||
| } /* else drop on floor */ | } /* else drop on floor */ | ||||
| sc->thre_int_pending = true; | sc->thre_int_pending = true; | ||||
| break; | break; | ||||
| case REG_IER: | case REG_IER: | ||||
| /* | |||||
| * Assert an interrupt if re-enabling the THRE intr, since we | |||||
| * always report THRE as active in the status register. | |||||
| */ | |||||
| if ((sc->ier & IER_ETXRDY) == 0 && | |||||
| (value & IER_ETXRDY) != 0) { | |||||
| sc->thre_int_pending = true; | |||||
| } | |||||
| /* | /* | ||||
| * Apply mask so that bits 4-7 are 0 | * Apply mask so that bits 4-7 are 0 | ||||
| * Also enables bits 0-3 only if they're 1 | * Also enables bits 0-3 only if they're 1 | ||||
| */ | */ | ||||
| sc->ier = value & 0x0F; | sc->ier = value & 0x0F; | ||||
| break; | break; | ||||
| case REG_FCR: | case REG_FCR: | ||||
| /* | /* | ||||
| ▲ Show 20 Lines • Show All 260 Lines • Show Last 20 Lines | |||||