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sys/mips/sibyte/sb_scd.c
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#include "sb_scd.h" | #include "sb_scd.h" | ||||
/* | #define sb_store64(addr, val) writeq((uint64_t *)(intptr_t)(addr), (val)) | ||||
* We compile a 32-bit kernel to run on the SB-1 processor which is a 64-bit | #define sb_load64(addr) readq((uint64_t *)(intptr_t)(addr)) | ||||
* processor. It has some registers that must be accessed using 64-bit load | |||||
* and store instructions. | |||||
* | |||||
* We use the mips_ld() and mips_sd() functions to do this for us. | |||||
*/ | |||||
#define sb_store64(addr, val) mips3_sd((uint64_t *)(uintptr_t)(addr), (val)) | |||||
#define sb_load64(addr) mips3_ld((uint64_t *)(uintptr_t)(addr)) | |||||
/* | /* | ||||
* System Control and Debug (SCD) unit on the Sibyte ZBbus. | * System Control and Debug (SCD) unit on the Sibyte ZBbus. | ||||
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