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* Build the TTBR0 maps.		* Build the TTBR0 maps.
*/		*/
add x27, x24, #PAGE_SIZE		add x27, x24, #PAGE_SIZE

mov x6, x27 /* The initial page table */		mov x6, x27 /* The initial page table */
#if defined(SOCDEV_PA) && defined(SOCDEV_VA)		#if defined(SOCDEV_PA) && defined(SOCDEV_VA)
/* Create a table for the UART */		/* Create a table for the UART */
mov x7, #DEVICE_MEM		mov x7, #DEVICE_MEM
mov x8, #(SOCDEV_VA) /* VA start */		ldr x8, =(SOCDEV_VA) /* VA start */
mov x9, #(SOCDEV_PA) /* PA start */		ldr x9, =(SOCDEV_PA) /* PA start */
mov x10, #1		mov x10, #1
bl build_l1_block_pagetable		bl build_l1_block_pagetable
#endif		#endif

/* Create the VA = PA map */		/* Create the VA = PA map */
mov x7, #NORMAL_UNCACHED /* Uncached as it's only needed early on */		mov x7, #NORMAL_UNCACHED /* Uncached as it's only needed early on */
mov x9, x27		mov x9, x27
mov x8, x9 /* VA start (== PA start) */		mov x8, x9 /* VA start (== PA start) */
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