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	#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G (1u << 20)			#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G (1u << 20)
	#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G (1u << 21)			#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G (1u << 21)
	#define IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE (1u << 25)			#define IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE (1u << 25)
	#define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24) /* X552 reg field only */			#define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24) /* X552 reg field only */
	#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3			#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3
	#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD \			#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD \
	(0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)			(0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)

				#define IXGBE_REQUEST_TASK_MOD 0x01
				#define IXGBE_REQUEST_TASK_MSF 0x02
				#define IXGBE_REQUEST_TASK_MBX 0x04
				#define IXGBE_REQUEST_TASK_FDIR 0x08
				#define IXGBE_REQUEST_TASK_PHY 0x10
				#define IXGBE_REQUEST_TASK_LSC 0x20

	#endif /* _IXGBE_TYPE_H_ */			#endif /* _IXGBE_TYPE_H_ */