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Differential D18893 Diff 53221 sys/amd64/include/pmap.h

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sys/amd64/include/pmap.h

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#define X86_PG_M 0x040 /* D Dirty */ #define X86_PG_M 0x040 /* D Dirty */
#define X86_PG_PS 0x080 /* PS Page size (0=4k,1=2M) */ #define X86_PG_PS 0x080 /* PS Page size (0=4k,1=2M) */
#define X86_PG_PTE_PAT 0x080 /* PAT PAT index */ #define X86_PG_PTE_PAT 0x080 /* PAT PAT index */
#define X86_PG_G 0x100 /* G Global */ #define X86_PG_G 0x100 /* G Global */
#define X86_PG_AVAIL1 0x200 /* / Available for system */ #define X86_PG_AVAIL1 0x200 /* / Available for system */
#define X86_PG_AVAIL2 0x400 /* < programmers use */ #define X86_PG_AVAIL2 0x400 /* < programmers use */
#define X86_PG_AVAIL3 0x800 /* \ */ #define X86_PG_AVAIL3 0x800 /* \ */
#define X86_PG_PDE_PAT 0x1000 /* PAT PAT index */ #define X86_PG_PDE_PAT 0x1000 /* PAT PAT index */
#define X86_PG_PKU(idx) ((pt_entry_t)idx << 59)
#define X86_PG_NX (1ul<<63) /* No-execute */ #define X86_PG_NX (1ul<<63) /* No-execute */
#define X86_PG_AVAIL(x) (1ul << (x)) #define X86_PG_AVAIL(x) (1ul << (x))
/* Page level cache control fields used to determine the PAT type */ /* Page level cache control fields used to determine the PAT type */
#define X86_PG_PDE_CACHE (X86_PG_PDE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD) #define X86_PG_PDE_CACHE (X86_PG_PDE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD)
#define X86_PG_PTE_CACHE (X86_PG_PTE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD) #define X86_PG_PTE_CACHE (X86_PG_PTE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD)
/* Protection keys indexes */
#define PMAP_MAX_PKRU_IDX 0xf
#define X86_PG_PKU_MASK X86_PG_PKU(PMAP_MAX_PKRU_IDX)
/* /*
* Intel extended page table (EPT) bit definitions. * Intel extended page table (EPT) bit definitions.
*/ */
#define EPT_PG_READ 0x001 /* R Read */ #define EPT_PG_READ 0x001 /* R Read */
#define EPT_PG_WRITE 0x002 /* W Write */ #define EPT_PG_WRITE 0x002 /* W Write */
#define EPT_PG_EXECUTE 0x004 /* X Execute */ #define EPT_PG_EXECUTE 0x004 /* X Execute */
#define EPT_PG_IGNORE_PAT 0x040 /* IPAT Ignore PAT */ #define EPT_PG_IGNORE_PAT 0x040 /* IPAT Ignore PAT */
#define EPT_PG_PS 0x080 /* PS Page size */ #define EPT_PG_PS 0x080 /* PS Page size */
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#define PG_FRAME (0x000ffffffffff000ul) #define PG_FRAME (0x000ffffffffff000ul)
#define PG_PS_FRAME (0x000fffffffe00000ul) #define PG_PS_FRAME (0x000fffffffe00000ul)
/* /*
* Promotion to a 2MB (PDE) page mapping requires that the corresponding 4KB * Promotion to a 2MB (PDE) page mapping requires that the corresponding 4KB
* (PTE) page mappings have identical settings for the following fields: * (PTE) page mappings have identical settings for the following fields:
*/ */
#define PG_PTE_PROMOTE (PG_NX | PG_MANAGED | PG_W | PG_G | PG_PTE_CACHE | \ #define PG_PTE_PROMOTE (PG_NX | PG_MANAGED | PG_W | PG_G | PG_PTE_CACHE | \
PG_M | PG_A | PG_U | PG_RW | PG_V) PG_M | PG_A | PG_U | PG_RW | PG_V | PG_PKU_MASK)
/* /*
* Page Protection Exception bits * Page Protection Exception bits
*/ */
#define PGEX_P 0x01 /* Protection violation vs. not present */ #define PGEX_P 0x01 /* Protection violation vs. not present */
#define PGEX_W 0x02 /* during a Write cycle */ #define PGEX_W 0x02 /* during a Write cycle */
#define PGEX_U 0x04 /* access from User mode (UPL) */ #define PGEX_U 0x04 /* access from User mode (UPL) */
#define PGEX_RSV 0x08 /* reserved PTE field is non-zero */ #define PGEX_RSV 0x08 /* reserved PTE field is non-zero */
#define PGEX_I 0x10 /* during an instruction fetch */ #define PGEX_I 0x10 /* during an instruction fetch */
#define PGEX_PK 0x20 /* protection key violation */
#define PGEX_SGX 0x40 /* SGX-related */
/* /*
* undef the PG_xx macros that define bits in the regular x86 PTEs that * undef the PG_xx macros that define bits in the regular x86 PTEs that
* have a different position in nested PTEs. This is done when compiling * have a different position in nested PTEs. This is done when compiling
* code that needs to be aware of the differences between regular x86 and * code that needs to be aware of the differences between regular x86 and
* nested PTEs. * nested PTEs.
* *
* The appropriate bitmask will be calculated at runtime based on the pmap * The appropriate bitmask will be calculated at runtime based on the pmap
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#define PMAP_NO_CR3 (~0UL) #define PMAP_NO_CR3 (~0UL)
#ifndef LOCORE #ifndef LOCORE
#include <sys/queue.h> #include <sys/queue.h>
#include <sys/_cpuset.h> #include <sys/_cpuset.h>
#include <sys/_lock.h> #include <sys/_lock.h>
#include <sys/_mutex.h> #include <sys/_mutex.h>
#include <sys/_pctrie.h>
#include <sys/_rangeset.h>
#include <vm/_vm_radix.h> #include <vm/_vm_radix.h>
typedef u_int64_t pd_entry_t; typedef u_int64_t pd_entry_t;
typedef u_int64_t pt_entry_t; typedef u_int64_t pt_entry_t;
typedef u_int64_t pdp_entry_t; typedef u_int64_t pdp_entry_t;
typedef u_int64_t pml4_entry_t; typedef u_int64_t pml4_entry_t;
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Linesstruct pmap {
TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */ TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */
cpuset_t pm_active; /* active on cpus */ cpuset_t pm_active; /* active on cpus */
enum pmap_type pm_type; /* regular or nested tables */ enum pmap_type pm_type; /* regular or nested tables */
struct pmap_statistics pm_stats; /* pmap statistics */ struct pmap_statistics pm_stats; /* pmap statistics */
struct vm_radix pm_root; /* spare page table pages */ struct vm_radix pm_root; /* spare page table pages */
long pm_eptgen; /* EPT pmap generation id */ long pm_eptgen; /* EPT pmap generation id */
int pm_flags; int pm_flags;
struct pmap_pcids pm_pcids[MAXCPU]; struct pmap_pcids pm_pcids[MAXCPU];
struct rangeset pm_pkru;
}; };
/* flags */ /* flags */
#define PMAP_NESTED_IPIMASK 0xff #define PMAP_NESTED_IPIMASK 0xff
#define PMAP_PDE_SUPERPAGE (1 << 8) /* supports 2MB superpages */ #define PMAP_PDE_SUPERPAGE (1 << 8) /* supports 2MB superpages */
#define PMAP_EMULATE_AD_BITS (1 << 9) /* needs A/D bits emulation */ #define PMAP_EMULATE_AD_BITS (1 << 9) /* needs A/D bits emulation */
#define PMAP_SUPPORTS_EXEC_ONLY (1 << 10) /* execute only mappings ok */ #define PMAP_SUPPORTS_EXEC_ONLY (1 << 10) /* execute only mappings ok */
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boolean_t pmap_map_io_transient(vm_page_t *, vm_offset_t *, int, boolean_t); boolean_t pmap_map_io_transient(vm_page_t *, vm_offset_t *, int, boolean_t);
void pmap_unmap_io_transient(vm_page_t *, vm_offset_t *, int, boolean_t); void pmap_unmap_io_transient(vm_page_t *, vm_offset_t *, int, boolean_t);
void pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec); void pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec);
void pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva); void pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva);
void pmap_pti_pcid_invalidate(uint64_t ucr3, uint64_t kcr3); void pmap_pti_pcid_invalidate(uint64_t ucr3, uint64_t kcr3);
void pmap_pti_pcid_invlpg(uint64_t ucr3, uint64_t kcr3, vm_offset_t va); void pmap_pti_pcid_invlpg(uint64_t ucr3, uint64_t kcr3, vm_offset_t va);
void pmap_pti_pcid_invlrng(uint64_t ucr3, uint64_t kcr3, vm_offset_t sva, void pmap_pti_pcid_invlrng(uint64_t ucr3, uint64_t kcr3, vm_offset_t sva,
vm_offset_t eva); vm_offset_t eva);
int pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
int pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
u_int keyidx, int flags);
#endif /* _KERNEL */ #endif /* _KERNEL */
/* Return various clipped indexes for a given VA */ /* Return various clipped indexes for a given VA */
static __inline vm_pindex_t static __inline vm_pindex_t
pmap_pte_index(vm_offset_t va) pmap_pte_index(vm_offset_t va)
{ {
return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1)); return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
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