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Show First 20 Lines • Show All 1,222 Lines • ▼ Show 20 Lines	for (i = 0; i < adapter->num_tx_queues; i++, que++) {

/* Set the HW Tx Head and Tail indices */		/* Set the HW Tx Head and Tail indices */
IXGBE_WRITE_REG(&adapter->hw, IXGBE_VFTDH(j), 0);		IXGBE_WRITE_REG(&adapter->hw, IXGBE_VFTDH(j), 0);
IXGBE_WRITE_REG(&adapter->hw, IXGBE_VFTDT(j), 0);		IXGBE_WRITE_REG(&adapter->hw, IXGBE_VFTDT(j), 0);

/* Set Tx Tail register */		/* Set Tx Tail register */
txr->tail = IXGBE_VFTDT(j);		txr->tail = IXGBE_VFTDT(j);

txr->tx_rs_cidx = txr->tx_rs_pidx = txr->tx_cidx_processed = 0;		txr->tx_rs_cidx = txr->tx_rs_pidx;
		/* Initialize the last processed descriptor to be the end of
		* the ring, rather than the start, so that we avoid an
		* off-by-one error when calculating how many descriptors are
		* done in the credits_update function.
		*/
		txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
for (int k = 0; k < scctx->isc_ntxd[0]; k++)		for (int k = 0; k < scctx->isc_ntxd[0]; k++)
txr->tx_rsq[k] = QIDX_INVALID;		txr->tx_rsq[k] = QIDX_INVALID;

/* Set Ring parameters */		/* Set Ring parameters */
IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(j),		IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(j),
(tdba & 0x00000000ffffffffULL));		(tdba & 0x00000000ffffffffULL));
IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(j), (tdba >> 32));		IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(j), (tdba >> 32));
IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(j),		IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(j),
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