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head/sys/net/iflib.c
Show First 20 Lines • Show All 283 Lines • ▼ Show 20 Lines | typedef struct iflib_sw_tx_desc_array { | ||||
bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ | bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ | ||||
bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ | bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ | ||||
struct mbuf **ifsd_m; /* pkthdr mbufs */ | struct mbuf **ifsd_m; /* pkthdr mbufs */ | ||||
} if_txsd_vec_t; | } if_txsd_vec_t; | ||||
/* magic number that should be high enough for any hardware */ | /* magic number that should be high enough for any hardware */ | ||||
#define IFLIB_MAX_TX_SEGS 128 | #define IFLIB_MAX_TX_SEGS 128 | ||||
/* bnxt supports 64 with hardware LRO enabled */ | |||||
#define IFLIB_MAX_RX_SEGS 64 | |||||
#define IFLIB_RX_COPY_THRESH 128 | #define IFLIB_RX_COPY_THRESH 128 | ||||
#define IFLIB_MAX_RX_REFRESH 32 | #define IFLIB_MAX_RX_REFRESH 32 | ||||
/* The minimum descriptors per second before we start coalescing */ | /* The minimum descriptors per second before we start coalescing */ | ||||
#define IFLIB_MIN_DESC_SEC 16384 | #define IFLIB_MIN_DESC_SEC 16384 | ||||
#define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 | #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 | ||||
#define IFLIB_QUEUE_IDLE 0 | #define IFLIB_QUEUE_IDLE 0 | ||||
#define IFLIB_QUEUE_HUNG 1 | #define IFLIB_QUEUE_HUNG 1 | ||||
#define IFLIB_QUEUE_WORKING 2 | #define IFLIB_QUEUE_WORKING 2 | ||||
▲ Show 20 Lines • Show All 1,020 Lines • ▼ Show 20 Lines | |||||
_iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) | _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) | ||||
{ | { | ||||
if (err) | if (err) | ||||
return; | return; | ||||
*(bus_addr_t *) arg = segs[0].ds_addr; | *(bus_addr_t *) arg = segs[0].ds_addr; | ||||
} | } | ||||
int | int | ||||
iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) | iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) | ||||
{ | { | ||||
int err; | int err; | ||||
if_shared_ctx_t sctx = ctx->ifc_sctx; | |||||
device_t dev = ctx->ifc_dev; | device_t dev = ctx->ifc_dev; | ||||
KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); | |||||
err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ | err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ | ||||
sctx->isc_q_align, 0, /* alignment, bounds */ | align, 0, /* alignment, bounds */ | ||||
BUS_SPACE_MAXADDR, /* lowaddr */ | BUS_SPACE_MAXADDR, /* lowaddr */ | ||||
BUS_SPACE_MAXADDR, /* highaddr */ | BUS_SPACE_MAXADDR, /* highaddr */ | ||||
NULL, NULL, /* filter, filterarg */ | NULL, NULL, /* filter, filterarg */ | ||||
size, /* maxsize */ | size, /* maxsize */ | ||||
1, /* nsegments */ | 1, /* nsegments */ | ||||
size, /* maxsegsize */ | size, /* maxsegsize */ | ||||
BUS_DMA_ALLOCNOW, /* flags */ | BUS_DMA_ALLOCNOW, /* flags */ | ||||
NULL, /* lockfunc */ | NULL, /* lockfunc */ | ||||
Show All 31 Lines | |||||
fail_2: | fail_2: | ||||
bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); | bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); | ||||
fail_1: | fail_1: | ||||
bus_dma_tag_destroy(dma->idi_tag); | bus_dma_tag_destroy(dma->idi_tag); | ||||
fail_0: | fail_0: | ||||
dma->idi_tag = NULL; | dma->idi_tag = NULL; | ||||
return (err); | return (err); | ||||
} | |||||
int | |||||
iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) | |||||
{ | |||||
if_shared_ctx_t sctx = ctx->ifc_sctx; | |||||
KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); | |||||
return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); | |||||
} | } | ||||
int | int | ||||
iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) | iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) | ||||
{ | { | ||||
int i, err; | int i, err; | ||||
iflib_dma_info_t *dmaiter; | iflib_dma_info_t *dmaiter; | ||||
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