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sys/i386/i386/initcpu.c
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} | } | ||||
#endif | #endif | ||||
extern int elf32_nxstack; | extern int elf32_nxstack; | ||||
void | void | ||||
initializecpu(void) | initializecpu(void) | ||||
{ | { | ||||
uint64_t msr; | |||||
switch (cpu) { | switch (cpu) { | ||||
#ifdef I486_CPU | #ifdef I486_CPU | ||||
case CPU_BLUE: | case CPU_BLUE: | ||||
init_bluelightning(); | init_bluelightning(); | ||||
break; | break; | ||||
case CPU_486DLC: | case CPU_486DLC: | ||||
init_486dlc(); | init_486dlc(); | ||||
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#endif | #endif | ||||
default: | default: | ||||
break; | break; | ||||
} | } | ||||
if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { | if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { | ||||
load_cr4(rcr4() | CR4_FXSR | CR4_XMM); | load_cr4(rcr4() | CR4_FXSR | CR4_XMM); | ||||
cpu_fxsr = hw_instruction_sse = 1; | cpu_fxsr = hw_instruction_sse = 1; | ||||
} | } | ||||
#if defined(PAE) || defined(PAE_TABLES) | if (elf32_nxstack) { | ||||
if ((amd_feature & AMDID_NX) != 0) { | |||||
uint64_t msr; | |||||
msr = rdmsr(MSR_EFER) | EFER_NXE; | msr = rdmsr(MSR_EFER) | EFER_NXE; | ||||
wrmsr(MSR_EFER, msr); | wrmsr(MSR_EFER, msr); | ||||
pg_nx = PG_NX; | |||||
elf32_nxstack = 1; | |||||
} | } | ||||
#endif | |||||
} | } | ||||
void | void | ||||
initializecpucache(void) | initializecpucache(void) | ||||
{ | { | ||||
/* | /* | ||||
* CPUID with %eax = 1, %ebx returns | * CPUID with %eax = 1, %ebx returns | ||||
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