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head/sys/dev/iwn/if_iwnvar.h
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}; | }; | ||||
struct iwn_tx_data { | struct iwn_tx_data { | ||||
bus_dmamap_t map; | bus_dmamap_t map; | ||||
bus_addr_t cmd_paddr; | bus_addr_t cmd_paddr; | ||||
bus_addr_t scratch_paddr; | bus_addr_t scratch_paddr; | ||||
struct mbuf *m; | struct mbuf *m; | ||||
struct ieee80211_node *ni; | struct ieee80211_node *ni; | ||||
unsigned int remapped:1; | |||||
unsigned int long_retries:7; | |||||
#define IWN_LONG_RETRY_FW_OVERFLOW 0x10 | |||||
#define IWN_LONG_RETRY_LIMIT_LOG 7 | |||||
#define IWN_LONG_RETRY_LIMIT ((1 << IWN_LONG_RETRY_LIMIT_LOG) - 3) | |||||
}; | }; | ||||
struct iwn_tx_ring { | struct iwn_tx_ring { | ||||
struct iwn_dma_info desc_dma; | struct iwn_dma_info desc_dma; | ||||
struct iwn_dma_info cmd_dma; | struct iwn_dma_info cmd_dma; | ||||
struct iwn_tx_desc *desc; | struct iwn_tx_desc *desc; | ||||
struct iwn_tx_cmd *cmd; | struct iwn_tx_cmd *cmd; | ||||
struct iwn_tx_data data[IWN_TX_RING_COUNT]; | struct iwn_tx_data data[IWN_TX_RING_COUNT]; | ||||
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}; | }; | ||||
struct iwn_node { | struct iwn_node { | ||||
struct ieee80211_node ni; /* must be the first */ | struct ieee80211_node ni; /* must be the first */ | ||||
uint16_t disable_tid; | uint16_t disable_tid; | ||||
uint8_t id; | uint8_t id; | ||||
struct { | struct { | ||||
uint64_t bitmap; | uint64_t bitmap; | ||||
int short_retries; | |||||
int startidx; | int startidx; | ||||
int nframes; | |||||
} agg[IEEE80211_TID_SIZE]; | } agg[IEEE80211_TID_SIZE]; | ||||
}; | }; | ||||
struct iwn_calib_state { | struct iwn_calib_state { | ||||
uint8_t state; | uint8_t state; | ||||
#define IWN_CALIB_STATE_INIT 0 | #define IWN_CALIB_STATE_INIT 0 | ||||
#define IWN_CALIB_STATE_ASSOC 1 | #define IWN_CALIB_STATE_ASSOC 1 | ||||
#define IWN_CALIB_STATE_RUN 2 | #define IWN_CALIB_STATE_RUN 2 | ||||
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