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head/sys/dev/iwn/if_iwnreg.h
| Show First 20 Lines • Show All 1,372 Lines • ▼ Show 20 Lines | |||||
| #define IWN_AGG_TX_STATE_TEST_BAD_CRC32_MSK 0x100 | #define IWN_AGG_TX_STATE_TEST_BAD_CRC32_MSK 0x100 | ||||
| #define IWN_AGG_TX_STATE_RESPONSE_MSK 0x1ff | #define IWN_AGG_TX_STATE_RESPONSE_MSK 0x1ff | ||||
| #define IWN_AGG_TX_STATE_DUMP_TX_MSK 0x200 | #define IWN_AGG_TX_STATE_DUMP_TX_MSK 0x200 | ||||
| #define IWN_AGG_TX_STATE_DELAY_TX_MSK 0x400 | #define IWN_AGG_TX_STATE_DELAY_TX_MSK 0x400 | ||||
| #define IWN_AGG_TX_STATUS_MSK 0x00000fff | #define IWN_AGG_TX_STATUS_MSK 0x00000fff | ||||
| #define IWN_AGG_TX_TRY_MSK 0x0000f000 | #define IWN_AGG_TX_TRY_MSK 0x0000f000 | ||||
| #define IWN_AGG_TX_TRY_POS 12 | |||||
| #define IWN_AGG_TX_TRY_COUNT(status) \ | |||||
| (((status) & IWN_AGG_TX_TRY_MSK) >> IWN_AGG_TX_TRY_POS) | |||||
| #define IWN_AGG_TX_STATE_LAST_SENT_MSK \ | #define IWN_AGG_TX_STATE_LAST_SENT_MSK \ | ||||
| (IWN_AGG_TX_STATE_LAST_SENT_TTL_MSK | \ | (IWN_AGG_TX_STATE_LAST_SENT_TTL_MSK | \ | ||||
| IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK) | IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK) | ||||
| #define IWN_AGG_TX_STATE_IGNORE_MASK \ | |||||
| (IWN_AGG_TX_STATE_FEW_BYTES_MSK | \ | |||||
| IWN_AGG_TX_STATE_ABORT_MSK) | |||||
| /* # tx attempts for first frame in aggregation */ | /* # tx attempts for first frame in aggregation */ | ||||
| #define IWN_AGG_TX_STATE_TRY_CNT_POS 12 | #define IWN_AGG_TX_STATE_TRY_CNT_POS 12 | ||||
| #define IWN_AGG_TX_STATE_TRY_CNT_MSK 0xf000 | #define IWN_AGG_TX_STATE_TRY_CNT_MSK 0xf000 | ||||
| /* Command ID and sequence number of Tx command for this frame */ | /* Command ID and sequence number of Tx command for this frame */ | ||||
| #define IWN_AGG_TX_STATE_SEQ_NUM_POS 16 | #define IWN_AGG_TX_STATE_SEQ_NUM_POS 16 | ||||
| #define IWN_AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000 | #define IWN_AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000 | ||||
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