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Differential D18727 Diff 52544 head/sys/dev/rtwn/rtl8188e/pci/r88ee_init.c

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head/sys/dev/rtwn/rtl8188e/pci/r88ee_init.c

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Linesr88ee_init_intr(struct rtwn_softc *sc)
rtwn_write_4(sc, R88E_HIMRE, 0x00000000); rtwn_write_4(sc, R88E_HIMRE, 0x00000000);
} }
int int
r88ee_power_on(struct rtwn_softc *sc) r88ee_power_on(struct rtwn_softc *sc)
{ {
int ntries; int ntries;
/* Wait for power ready bit. */ /* Disable XTAL output for power saving. */
rtwn_setbits_1(sc, R88E_XCK_OUT_CTRL, R88E_XCK_OUT_CTRL_EN, 0);
/* Unlock ISO/CLK/Power control register. */
rtwn_setbits_2(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_APDM_HPDN, 0);
rtwn_write_1(sc, R92C_RSV_CTRL, 0);
/* Wait for power ready bit */
for (ntries = 0; ntries < 5000; ntries++) { for(ntries = 0; ntries < 5000; ntries++) {
if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
break; break;
rtwn_delay(sc, 10); rtwn_delay(sc, 10);
} }
if (ntries == 5000) { if (ntries == 5000) {
device_printf(sc->sc_dev, device_printf(sc->sc_dev,
"timeout waiting for chip power up\n"); "timeout waiting for chip power up\n");
return (ETIMEDOUT); return (ETIMEDOUT);
} }
/* Unlock ISO/CLK/Power control register. */
rtwn_write_1(sc, R92C_RSV_CTRL, 0);
/* Reset BB. */ /* Reset BB. */
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST, 0); R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
/* schmit trigger */ /* schmit trigger */
rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80); rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
/* Disable HWPDN. */ /* Disable HWPDN. */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_APDM_HPDN, 0, 1); R92C_APS_FSMCO_APDM_HPDN, 0, 1);
/* Disable WL suspend. */ /* Disable WL suspend. */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1); R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1);
/* Auto-enable WLAN */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
0, R92C_APS_FSMCO_APFM_ONMAC, 1); 0, R92C_APS_FSMCO_APFM_ONMAC, 1);
for (ntries = 0; ntries < 5000; ntries++) { for (ntries = 0; ntries < 5000; ntries++) {
if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
R92C_APS_FSMCO_APFM_ONMAC)) R92C_APS_FSMCO_APFM_ONMAC))
break; break;
rtwn_delay(sc, 10); rtwn_delay(sc, 10);
} }
if (ntries == 5000) if (ntries == 5000)
return (ETIMEDOUT); return (ETIMEDOUT);
rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04); rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
/* Enable LDO normal mode. */ /* Enable LDO normal mode. */
rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP, 0); rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP, 0);
rtwn_setbits_1(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_PDN_EN);
rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL_EXT + 1, 0, 0x02);
rtwn_setbits_1(sc, R92C_SYS_CLKR, 0, 0x08);
rtwn_setbits_2(sc, R92C_GPIO_MUXCFG, R92C_GPIO_MUXCFG_ENSIC, 0);
/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
rtwn_write_2(sc, R92C_CR, 0); rtwn_write_2(sc, R92C_CR, 0);
rtwn_setbits_2(sc, R92C_CR, 0, rtwn_setbits_2(sc, R92C_CR, 0,
R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN | R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN | R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) | ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
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