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Differential D15692 Diff 52473 head/sys/dev/rtwn/rtl8188e/r88e_reg.h

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head/sys/dev/rtwn/rtl8188e/r88e_reg.h

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#define R88E_MACID_NO_LINK 0x484 #define R88E_MACID_NO_LINK 0x484
#define R88E_TX_RPT_CTRL 0x4ec #define R88E_TX_RPT_CTRL 0x4ec
#define R88E_TX_RPT_MACID_MAX 0x4ed #define R88E_TX_RPT_MACID_MAX 0x4ed
#define R88E_TX_RPT_TIME 0x4f0 #define R88E_TX_RPT_TIME 0x4f0
#define R88E_SCH_TXCMD 0x5f8 #define R88E_SCH_TXCMD 0x5f8
/* Bits for R88E_HIMR. */ /* Bits for R88E_HIMR. */
#define R88E_HIMR_CPWM 0x00000100 #define R88E_HIMR_ROK 0x00000001 /* receive DMA OK */
#define R88E_HIMR_CPWM2 0x00000200 #define R88E_HIMR_RDU 0x00000002 /* Rx descriptor unavailable */
#define R88E_HIMR_TBDER 0x04000000 #define R88E_HIMR_VODOK 0x00000004 /* AC_VO DMA OK */
#define R88E_HIMR_PSTIMEOUT 0x20000000 #define R88E_HIMR_VIDOK 0x00000008 /* AC_VI DMA OK */
#define R88E_HIMR_BEDOK 0x00000010 /* AC_BE DMA OK */
#define R88E_HIMR_BKDOK 0x00000020 /* AC_BK DMA OK */
#define R88E_HIMR_MGNTDOK 0x00000040 /* management queue DMA OK */
#define R88E_HIMR_HIGHDOK 0x00000080 /* high queue DMA OK */
#define R88E_HIMR_CPWM 0x00000100 /* CPU power mode intr 1 */
#define R88E_HIMR_CPWM2 0x00000200 /* CPU power mode intr 2 */
#define R88E_HIMR_C2HCMD 0x00000400 /* C2H command interrupt */
#define R88E_HIMR_HISR 0x00000800 /* (HISR & HIMR) != 0 */
#define R88E_HIMR_ATIMEND 0x00001000 /* ATIM window end interrupt */
#define R88E_HIMR_HSISR 0x00008000 /* (HSIMR & HSISR) != 0 */
#define R88E_HIMR_BCNDERR 0x00010000 /* beacon queue DMA error */
#define R88E_HIMR_BCNINT 0x00100000 /* beacon DMA interrupt 0 */
#define R88E_HIMR_TSF32 0x01000000 /* TSF 32 bit interrupt */
#define R88E_HIMR_TBDOK 0x02000000 /* beacon transmit OK */
#define R88E_HIMR_TBDER 0x04000000 /* beacon transmit error */
#define R88E_HIMR_GTIMER3 0x08000000 /* GTIMER3 interrupt */
#define R88E_HIMR_GTIMER4 0x10000000 /* GTIMER4 interrupt */
#define R88E_HIMR_PSTIMEOUT 0x20000000 /* powersave timeout */
#define R88E_HIMR_TXRPT 0x40000000 /* Tx report interrupt */
/* Bits for R88E_HIMRE.*/ /* Bits for R88E_HIMRE.*/
#define R88E_HIMRE_RXFOVW 0x00000100 #define R88E_HIMRE_RXFOVW 0x00000100 /* receive FIFO overflow */
#define R88E_HIMRE_TXFOVW 0x00000200 #define R88E_HIMRE_TXFOVW 0x00000200 /* transmit FIFO overflow */
#define R88E_HIMRE_RXERR 0x00000400 #define R88E_HIMRE_RXERR 0x00000400 /* receive error */
#define R88E_HIMRE_TXERR 0x00000800 #define R88E_HIMRE_TXERR 0x00000800 /* transmit error */
#define R88E_HIMRE_BCNDOK1 0x00004000 /* beacon queue DMA OK (1) */
#define R88E_HIMRE_BCNDOK2 0x00008000 /* beacon queue DMA OK (2) */
#define R88E_HIMRE_BCNDOK3 0x00010000 /* beacon queue DMA OK (3) */
#define R88E_HIMRE_BCNDOK4 0x00020000 /* beacon queue DMA OK (4) */
#define R88E_HIMRE_BCNDOK5 0x00040000 /* beacon queue DMA OK (5) */
#define R88E_HIMRE_BCNDOK6 0x00080000 /* beacon queue DMA OK (6) */
#define R88E_HIMRE_BCNDOK7 0x00100000 /* beacon queue DMA OK (7) */
#define R88E_HIMRE_BCNDMAINT1 0x00200000 /* beacon DMA interrupt 1 */
#define R88E_HIMRE_BCNDMAINT2 0x00400000 /* beacon DMA interrupt 2 */
#define R88E_HIMRE_BCNDMAINT3 0x00800000 /* beacon DMA interrupt 3 */
#define R88E_HIMRE_BCNDMAINT4 0x01000000 /* beacon DMA interrupt 4 */
#define R88E_HIMRE_BCNDMAINT5 0x02000000 /* beacon DMA interrupt 5 */
#define R88E_HIMRE_BCNDMAINT6 0x04000000 /* beacon DMA interrupt 6 */
#define R88E_HIMRE_BCNDMAINT7 0x08000000 /* beacon DMA interrupt 7 */
/* Bits for R88E_TX_RPT_CTRL. */ /* Bits for R88E_TX_RPT_CTRL. */
#define R88E_TX_RPT1_ENA 0x01 #define R88E_TX_RPT1_ENA 0x01
#define R88E_TX_RPT2_ENA 0x02 #define R88E_TX_RPT2_ENA 0x02
/* Bits for R92C_MBID_NUM. */ /* Bits for R92C_MBID_NUM. */
#define R88E_MBID_TXBCN_RPT(id) (0x08 << (id)) #define R88E_MBID_TXBCN_RPT(id) (0x08 << (id))
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