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Differential D18276 Diff 51409 head/sys/dev/sfxge/common/ef10_nic.c

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head/sys/dev/sfxge/common/ef10_nic.c

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ef10_nic_get_port_mode_bandwidth( ef10_nic_get_port_mode_bandwidth(
__in uint32_t port_mode, __in uint32_t port_mode,
__out uint32_t *bandwidth_mbpsp) __out uint32_t *bandwidth_mbpsp)
{ {
uint32_t bandwidth; uint32_t bandwidth;
efx_rc_t rc; efx_rc_t rc;
switch (port_mode) { switch (port_mode) {
case TLV_PORT_MODE_10G: case TLV_PORT_MODE_1x1_NA: /* mode 0 */
bandwidth = 10000; bandwidth = 10000;
break; break;
case TLV_PORT_MODE_10G_10G: case TLV_PORT_MODE_1x1_1x1: /* mode 2 */
bandwidth = 10000 * 2; bandwidth = 10000 * 2;
break; break;
case TLV_PORT_MODE_10G_10G_10G_10G: case TLV_PORT_MODE_4x1_NA: /* mode 4 */
case TLV_PORT_MODE_10G_10G_10G_10G_Q: case TLV_PORT_MODE_2x1_2x1: /* mode 5 */
case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2: case TLV_PORT_MODE_NA_4x1: /* mode 8 */
case TLV_PORT_MODE_10G_10G_10G_10G_Q2:
bandwidth = 10000 * 4; bandwidth = 10000 * 4;
break; break;
case TLV_PORT_MODE_40G: /* Legacy Medford-only mode. Do not use (see bug63270) */
case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2: /* mode 9 */
bandwidth = 10000 * 4;
break;
case TLV_PORT_MODE_1x4_NA: /* mode 1 */
bandwidth = 40000; bandwidth = 40000;
break; break;
case TLV_PORT_MODE_40G_40G: case TLV_PORT_MODE_1x4_1x4: /* mode 3 */
bandwidth = 40000 * 2; bandwidth = 40000 * 2;
break; break;
case TLV_PORT_MODE_40G_10G_10G: case TLV_PORT_MODE_1x4_2x1: /* mode 6 */
case TLV_PORT_MODE_10G_10G_40G: case TLV_PORT_MODE_2x1_1x4: /* mode 7 */
bandwidth = 40000 + (10000 * 2); bandwidth = 40000 + (10000 * 2);
break; break;
default: default:
rc = EINVAL; rc = EINVAL;
goto fail1; goto fail1;
} }
*bandwidth_mbpsp = bandwidth; *bandwidth_mbpsp = bandwidth;
▲ Show 20 Lines • Show All 1,297 Lines • ▼ Show 20 Linesstatic struct ef10_external_port_map_s {
* cage. * cage.
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 2 * port 1 -> cage 2
* port 2 -> cage 3 * port 2 -> cage 3
* port 3 -> cage 4 * port 3 -> cage 4
*/ */
{ {
EFX_FAMILY_MEDFORD, EFX_FAMILY_MEDFORD,
(1U << TLV_PORT_MODE_10G) | /* mode 0 */ (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
(1U << TLV_PORT_MODE_10G_10G), /* mode 2 */ (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */
1, /* ports per cage */ 1, /* ports per cage */
1 /* first cage */ 1 /* first cage */
}, },
/* /*
* Modes that on Medford allocate 2 adjacent port numbers to each * Modes that on Medford allocate 2 adjacent port numbers to each
* cage. * cage.
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 1 * port 1 -> cage 1
* port 2 -> cage 2 * port 2 -> cage 2
* port 3 -> cage 2 * port 3 -> cage 2
*/ */
{ {
EFX_FAMILY_MEDFORD, EFX_FAMILY_MEDFORD,
(1U << TLV_PORT_MODE_40G) | /* mode 1 */ (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
(1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */ (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
(1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */ (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */
(1U << TLV_PORT_MODE_10G_10G_40G) | /* mode 7 */ (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
/* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */ /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */
(1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */ (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */
2, /* ports per cage */ 2, /* ports per cage */
1 /* first cage */ 1 /* first cage */
}, },
/* /*
* Modes that on Medford allocate 4 adjacent port numbers to each * Modes that on Medford allocate 4 adjacent port numbers to each
* connector, starting on cage 1. * connector, starting on cage 1.
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 1 * port 1 -> cage 1
* port 2 -> cage 1 * port 2 -> cage 1
* port 3 -> cage 1 * port 3 -> cage 1
*/ */
{ {
EFX_FAMILY_MEDFORD, EFX_FAMILY_MEDFORD,
(1U << TLV_PORT_MODE_10G_10G_10G_10G_Q) | /* mode 5 */ (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 5 */
/* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */ /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */
(1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1), /* mode 4 */ (1U << TLV_PORT_MODE_4x1_NA), /* mode 4 */
4, /* ports per cage */ 4, /* ports per cage */
1 /* first cage */ 1 /* first cage */
}, },
/* /*
* Modes that on Medford allocate 4 adjacent port numbers to each * Modes that on Medford allocate 4 adjacent port numbers to each
* connector, starting on cage 2. * connector, starting on cage 2.
* port 0 -> cage 2 * port 0 -> cage 2
* port 1 -> cage 2 * port 1 -> cage 2
* port 2 -> cage 2 * port 2 -> cage 2
* port 3 -> cage 2 * port 3 -> cage 2
*/ */
{ {
EFX_FAMILY_MEDFORD, EFX_FAMILY_MEDFORD,
(1U << TLV_PORT_MODE_10G_10G_10G_10G_Q2), /* mode 8 */ (1U << TLV_PORT_MODE_NA_4x1), /* mode 8 */
4, /* ports per cage */ 4, /* ports per cage */
2 /* first cage */ 2 /* first cage */
}, },
/* /*
* Modes that on Medford2 allocate each port number to a separate * Modes that on Medford2 allocate each port number to a separate
* cage. * cage.
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 2 * port 1 -> cage 2
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